Datasheet

Data Sheet AD7091
Rev. A | Page 15 of 20
SERIAL INTERFACE
The AD7091 serial interface consists of four signals: SCLK,
SDO,
CONVST
, and
CS
. The serial interface is used to access
data from the result register and to control the modes of oper-
ation of the device.
 The SCLK pin is the serial clock input for the device.
 The SDO pin outputs the conversion result; data transfers
take place with respect to SCLK.
 The
CONVST
pin is used to initiate the conversion process
and to select the mode of operation of the AD7091 (see the
Modes of Operation section).
 The
CS
pin is used to frame the data. The falling edge of
CS
takes the SDO line out of a high impedance state. A rising
edge on
CS
returns the SDO line to a high impedance state.
The logic level of
CS
at the end of a conversion determines
whether the busy indicator is enabled. This feature affects the
propagation of the MSB with respect to
CS
and SCLK.
BUSY INDICATOR ENABLED
When the busy indicator is enabled, the SDO pin can be used as
an interrupt signal to indicate that a conversion is complete. The
connection diagram for this configuration is shown in Figure 25.
Note that a pull-up resistor to V
DD
is required on the SDO pin.
DATA IN
IRQ
CLK
CONVERT
V
DD
DIGITAL HOST
100kΩ
CONVST
SCLK
SDO
CS
AD7091
CS1
10494-023
Figure 25. Connection Diagram with Busy Indicator
The busy indicator allows the host to detect when the SDO
pin exits the three-state condition after the end of a conversion.
When the busy indicator is enabled, 13 SCLK cycles are required:
12 clock cycles to propagate the data and an additional clock cycle
to return the SDO pin to the three-state condition.
To enable the busy indicator feature, a conversion must first
be started. A high-to-low transition on
CONVST
initiates a
conversion. This transition places the track-and-hold into hold
mode and samples the analog input at this point. If the user does
not want the AD7091 to enter power-down mode,
CONVST
should be taken high before the end of the conversion.
A conversion requires 650 ns to complete. When the conversion
process is finished, the track-and-hold returns to track mode.
Before the end of a conversion, pull
CS
low to enable the busy
indicator (see Figure 26).
The conversion result is shifted out of the device as a 12-bit
word under the control of SCLK and the logic level of
CS
at the
end of a conversion. At the end of a conversion, SDO is driven
low. SDO remains low until the MSB (DB11) of the conversion
result is clocked out on the first falling edge of SCLK. DB10 to
DB0 are shifted out on the subsequent falling edges of SCLK.
The 13
th
SCLK falling edge returns SDO to a high impedance
state. Data is propagated on SCLK falling edges and is valid on
both the rising and falling edges of the next SCLK. The timing
diagram for this operation is shown in Figure 26.
If another conversion is required, pull
CONVST
low again and
repeat the cycle.
THREE-STATE
THREE-STATE
CS
SCLK
1
5
12
2
34
DB11 DB10 DB9 DB2 DB1
DB0
t
2
t
4
t
3
t
5
t
6
DB8 DB7
SDO
CONVST
EOC
NOTES
1. EOC IS THE END OF A CONVERSION.
t
1
10 11
t
9
t
QUIET
t
7
t
8
13
10494-024
Figure 26. Serial Port Timing with Busy Indicator