Datasheet

AD5821A
Rev. 0 | Page 3 of 16
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (R
L
) = 25 Ω connected to V
DD
. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 1.
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE
V
DD
= 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V
with reduced performance
Resolution 10 Bits 117 μA/LSB
Relative Accuracy
2
±1.5 ±4 LSB
Differential Nonlinearity
2, 3
±1 LSB Guaranteed monotonic over all codes
Zero-Code Error
2, 4
0 0.5 1 mA All 0s loaded to DAC
Offset Error @ Code 16
2
0.5 mA
Gain Error
2
±0.6 % of FSR at 25°C
Offset Error Drift
4, 5
10 μA/°C
Gain Error Drift
2, 5
±0.2 ±0.5 LSB/°C
OUTPUT CHARACTERISTICS
Minimum Sink Current
4
3 mA
Maximum Sink Current 120 mA
Output Current During XSHUTDOWN
5
80 nA XSHUTDOWN = 0
Output Compliance
5
0.6 V
DD
V
Output voltage range over which maximum 120 mA
sink current is available
Output Compliance
5
0.48 V
DD
V
Output voltage range over which 90 mA sink current
is available
Power-Up Time
5
20 μs To 10% of FS, coming out of power-down mode; V
DD
= 5 V
LOGIC INPUTS (XSHUTDOWN)
5
Input Current ±1 μA
Input Low Voltage, V
INL
0.54 V V
DD
= 2.7 V to 5.5 V
Input High Voltage, V
INH
1.26 V V
DD
= 2.7 V to 5.5 V
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)
5
Input Low Voltage, V
INL
−0.3 +0.54 V V
DD
= 2.7 V to 3.6 V
Input High Voltage, V
INH
1.26 V
DD
+ 0.3 V V
DD
= 2.7 V to 3.6 V
Input Low Voltage, V
INL
−0.3 +0.54 V V
DD
= 3.6 V to 5.5 V
Input High Voltage, V
INH
1.4 V
DD
+ 0.3 V V
DD
= 3.6 V to 5.5 V
Input Leakage Current, I
IN
±1 μA V
IN
= 0 V to V
DD
Input Hysteresis, V
HYST
0.05 V
DD
V
Digital Input Capacitance, C
IN
6 pF
Glitch Rejection
6
50 ns Pulse width of spike suppressed
POWER REQUIREMENTS
V
DD
2.7 5.5 V
I
DD
(Normal Mode) 0.5 1 mA I
DD
specification is valid for all DAC codes;
V
INH
= 1.8 V, V
INL
= GND, V
DD
= 2.7 V to 3.6 V
I
DD
(Power-Down Mode)
7
0.5 μA V
INH
= 1.8 V, V
INL
= GND, V
DD
= 3 V
1
Temperature range for the B version is −30°C to +85°C.
2
See the Terminology section.
3
Linearity is tested using a reduced code range: Code 32 to Code 1023.
4
To achieve near zero output current, use the power-down feature.
5
Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V.
6
Input filtering on both the SCL and the SDA inputs suppress noise spikes that are less than 50 ns.
7
XSHUTDOWN is active low.