Datasheet

UG-244 Evaluation Board User Guide
Rev. B | Page 4 of 16
Connector J11 Pin Descriptions
2
1
4
3
6
5
8
7
10
9
12
11
09633-100
Figure 2. Connector J11 Pin Configuration
Table 4. Connector J11 Pin Descriptions
1
Pin No.
Description
1
DV
DD
2 DGND
3
SYNC
4 SCLK
5 SDIN
6 SDO (output)
7
LDAC
8 CLEAR
9 POC (AD5755 and AD5755-1)
10
RESET
11
FAULT
(output)
12 ALERT (output)
1
The SDP board must be disconnected when using the J11 connector.
OUTPUT CONNECTORS
There are five connectors per channel on the EVAL-AD575xSDZ
PCB. The output connectors are used as outlined in Table 5,
Table 6, and Table 7.
Table 5. On-Board Connectors for AD5755
Connector Function
GND There is a per-channel connection to AGND.
A1, B1, C1, D1 I
OUT
output for Channel A, Channel B,
Channel C, and Channel D, respectively.
A2, B2, C2, D2 −V
SENSE
input for Channel A, Channel B,
Channel C, and Channel D, respectively.
A3, B3, C3, D3 V
OUT
output for Channel A, Channel B,
Channel C, and Channel D, respectively.
A4, B4, C4, D4 +V
SENSE
input for Channel A, Channel B,
Channel C, and Channel D, respectively.
Table 6. On-Board Connectors for AD5757
Connector Function
GND There is a per-channel connection to AGND.
A1, B1, C1, D1 I
OUT
output for Channel A, Channel B,
Channel C, and Channel D, respectively.
A2, B2, C2, D2 CHART input for Channel A, Channel B,
Channel C, and Channel D, respectively. HART
signals should be capacitively coupled onto
these pins as described in the AD5757 data
sheet.
A4, B3, C3, D4 Connection to the IGATEx pin
A3, B4, C4, D3 Not used.
Table 7. On-Board Connectors for AD5755-1
Connector Function
GND There is a per-channel connection to AGND.
A1, B1, C1, D1 I
OUT
output for Channel A, Channel B,
Channel C, and Channel D, respectively.
A2, B2, C2, D2 CHART input for Channel A, Channel B, Channel
C, and Channel D, respectively. HART signals
should be capacitively coupled onto these pins
as described in the AD5755-1 data sheet.
A3, B3, C3, D3 V
OUT
output for Channel A, Channel B, Channel
C, and Channel D, respectively.
A4, B4, C4, D4
+V
SENSE
input for Channel A, Channel B, Channel
C, and Channel D, respectively.
DC-TO-DC BOOST
Each channel has a dc-to-dc boost converter. This consists of a
Schottky diode, inductor, and a low ESR, high voltage capacitor.
A low-pass RC filter is also included on a per-channel basis.
Table 8. DC-to-DC Circuitry
Symbol Component Value Manufacturer
L
DCDC
XAL4040-103 10 µH Coilcraft
C
DCDC
GRM32ER71H475KA88L 4.7 µF Murata
D
DCDC
PMEG3010BEA 0.38 V
F
NXP
R
FILTE R
N/A 10 Ω N/A
C
FILTER
N/A 0.1 µF N/A
The L
DCDC
10 µH inductor provides the best performance at the
410 kHz switching frequency. Consult the AD5755, AD5755-1
,
AD5757, or data sheet for more information on the dc-to-dc
converter circuitry.
AV
CC
C
IN
L
DCDC
D
DCDC
C
DCDC
C
FILTER
R
FILTER
SW
x
V
BOOST_X
09633-002
Figure 3. DC-to-DC Converter Circuitry
PATCHWORK
Patchwork is included on the E VA L -AD575xSDZ near the
output connectors. This is connected in rows with one row
connected to AGND per channel and one row connected to
I
OUT
per channel. All other rows are left floating.
When evaluating the EVAL-AD5757SDZ, the patchwork gives
access to the drain, gate and source of a discreet PMOS trans-
istor which can be used to evaluate the Igate functionality.
SYSTEM DEMONSTRATION PLATFORM (SDP)
The E VA L -AD575xSDZ board can connect to the SDP board
via the J9 connector. The SDP is a hardware and software
platform that provides a means to communicate from the PC
to supported Analog Devices products and systems that require
digital control and/or readback.The SDP has a Blackfin®
(BF527) at its core. This has on-chip USB 2.0 capabilities as well
as many external interface ports, such as SPI, SPORT, I
2
C, and a
16-bit parallel interface. See Figure 20 for connections made to
the SDP board.