Datasheet

AD5750/AD5750-1
Rev. C | Page 9 of 36
Timing Diagrams
D15
12 16
D0
t
1
t
2
t
5
t
8
t
7
t
3
SCLK
SYNC
SDIN
CLEA
R
VOUT
t
10
t
9
t
13
RESET
t
4
t
6
07268-003
Figure 2. Write Mode Timing Diagram
SCLK
SDIN
SDO
SYNC
A2 A1 A0 R = 1 0 X X X X X X X X X X X
X X X X X R3 R2 R1 R0 CLRSEL OUTEN RSET
PEC
ERROR
OVER
TEMP
IOUT
FAULT
VOUT
FAULT
12 16
t
11
t
12
0
7268-004
Figure 3. Readback Mode Timing Diagram