Datasheet

AD5750/AD5750-1
Rev. C | Page 8 of 36
TIMING CHARACTERISTICS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: R
LOAD
= 2 kΩ, C
L
= 200 pF, IOUT: R
LOAD
=
300 Ω. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Description
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
5 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
10 ns min
16
th
SCLK falling edge to SYNC rising edge (on 24
th
SCLK falling edge if using PEC)
t
6
5 ns min
Minimum SYNC
high time (write mode)
t
7
5 ns min Data setup time
t
8
5 ns min Data hold time
t
9
, t
10
1.5 μs max CLEAR pulse low/high activation time
t
11
5 ns min
Minimum SYNC
high time (read mode)
t
12
40 ns max SCLK rising edge to SDO valid (SDO C
L
= 15 pF)
t
13
10 ns min
RESET
pulse low time
1
Guaranteed by characterization, but not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.