Datasheet

AD5750/AD5750-1
Rev. C | Page 15 of 36
12
10
8
6
4
2
0
2722171272–3–8
VOLTAGE (V)
TIME (µs)
07268-117
Figure 17. Full-Scale Positive Step
12
10
8
6
4
2
0
2722171272–3–8
VOLTAGE (V)
TIME (µs)
07268-118
Figure 18. Full-Scale Negative Step
40
35
30
25
20
15
10
5
0
–5
2.52.01.51.00.50–0.5–1.0
V
OUT
(mV)
TIME (ms)
07268-119
Figure 19. V
OUT
vs. Time on Power-Up, Load = 2 kΩ || 200 pF
CH1 5.00V CH2 20.0mV
B
W
M1.0µs A CH1 3.00V
1
2
0
7268-120
Figure 20. V
OUT
Enable Glitch, Load = 2 kΩ || 1 nF
5µV/DIV 1s/DIV
07268-121
Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
100µV/DIV 1s/DIV
07268-122
Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth)