Datasheet

AD5601/AD5611/AD5621 Data Sheet
Rev. G | Page 20 of 24
OUTLINE DIMENSIONS
Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2.00 × 3.00 mm Body, Very Very Thin, Dual Lead
(CP-6-5)
Dimensions shown in millimeters
1
.
30
B
SC
COMPLIANT TO JEDEC STANDARDS MO-203-AB
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2
.4
0
2
.1
0
1
.8
0
1
.
35
1.
25
1
.
15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0
.
22
0.08
3
1 2
46
5
0
.6
5 B
S
C
COPLANA
RI
TY
0.1
0
SEATING
PLANE
0.30
0.15
1.50
1.40
1.30
0.45
0.40
0.35
TOP VIEW
6
1
4
3
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 MAX
0.00 MIN
0.65 REF
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
03-29-2012-B
2.10
2.00
1.90
3.10
3.00
2.90
COMPLIANT TO JEDEC STANDARDS MO-229
COPLANARITY
0.08
0.20 MIN
0.35
0.30
0.25