Datasheet

Data Sheet AD5560
Rev. D | Page 55 of 68
Address Register Default Data Bits, MSB First
0x3C CPH DAC c EXT Range 1 0x8000 D15 to D0.
0x3D DGS DAC 0x3333 D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
0x3E Ramp end code 0x0000 D15 to D0;
this is the ramp end code. The ramp start code is the code that is in the FIN
DAC register.
0x3F Ramp step size 0x0001 0000 0000 D6 to D0.
D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference,
16 LSB = 6.1 mV.
For example,
000 0000 = 16 LSBs (6.1 mV) step
000 0001 = 16 LSBs (6.1 mV) step
…
111 1111 = 2032 LSBs (775 mV) step.
0x40 RCLK divider 0x0001 0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
0000 0000 = ÷ 1
0000 0001 = ÷ 1
0000 0010 = ÷ 2
0000 0011 = ÷ 3
…
1111 1111 = ÷ 255
0x41 Enable ramp 0x0000 0xFFFF to enable.
0x42 Interrupt ramp 0x0000 0x0000 to interrupt.