Datasheet

AD5560 Data Sheet
Rev. D | Page 44 of 68
SERIAL INTERFACE
The AD5560 contains an SPI-compatible interface operating at
clock frequencies of up to 50 MHz. To minimize both the
power consumption of the device and on-chip digital noise, the
interface powers up fully only when the device is being written
to, that is, on the falling edge of
SYNC
.
SPI INTERFACE
The serial interface is 2.5 V LVTTL-compatible when operating
from a 2.3 V to 3.6 V DV
CC
supply. It is controlled by the
following four pins:
•
SYNC
(frame synchronization input)
• SDI (serial data input pin)
• SCLK (clocks data in and out of the device)
• SDO (serial data output pin for data readback)
SPI WRITE MODE
The AD5560 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which
is all registers except the DAC registers.
The serial word is 24 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5560 by clock pulses applied
to SCLK. The first falling edge of
SYNC
starts the write cycle.
At least 24 falling clock edges must be applied to SCLK to clock
in 24 bits of data before
SYNC
is taken high again.
The input register addressed is updated on the rising edge of
SYNC
. For another serial transfer to take place,
SYNC
must be
taken low again.
SDO OUTPUT
The SDO output in the AD5560 is a weak/slow output driver.
If using readback or the daisy-chain function, the frequency of
SCLK must be reduced so that SDO can operate properly. The
SCLK frequency is dependent on the DV
CC
supply voltage used;
see Table 2 for details and the following example:
Maximum SCLK = 12 MHz, then DV
CC
= 2.3 V to 2.7 V
Maximum SCLK = 15 MHz, then DV
CC
= 2.7 V to 3.3 V
Maximum SCLK = 20 MHz, then DV
CC
= 4.5 V to 5.5 V
RESET
FUNCTION
RESET
is a level-sensitive input. Bringing the
RESET
line low
resets the contents of all internal registers to their power-on
reset state. The falling edge of
RESET
initiates the reset process;
BUSY
goes low for the duration, returning high when the
RESET
process is complete. This sequence takes 300 µs
maximum. Do not write to the serial interface while
BUSY
is low handling a
RESET
command. When
BUSY
returns high,
normal operation resumes, and the status of the
RESET
pin is
ignored until it goes low again.
BUSY
FUNCTION
BUSY
is a digital open-drain output that indicates the status of
the AD5560. All writes drive the
BUSY
output low for some
period of time; however, events that use the calibration engine,
such as all DAC x1 writes, drive it lower for a longer period of
time while the calculations are completed.
For the DACs, the value of the internal data (x2) loaded to the
DAC data register is calculated each time the user writes new
data to the corresponding x1 register. During the calculation
of x2, the
BUSY
output goes low and x2 writes are pipelined;
therefore, x2 writes can still be presented to the device while
BUSY
is still low (see the Register Update Rates section). The
DAC outputs update immediately after
BUSY
goes high.
Writes to other registers must be handled differently and
should either watch the
BUSY
pin or be timed. While
BUSY
is low, the user can continue writing new data to any control
register, m register, or c register but should not complete the
writing process (
SYNC
returning high) until the
BUSY
signal
has returned high.
BUSY
also goes low during power-on reset, as well as when a
low level is detected on the
RESET
pin.
BUSY
writes to the system control register, compensation
register, alarm register, and diagnostic register; m or c registers
do not involve the calibration engine, thus speeding up writing
to the device.
LOAD
FUNCTION
The AD5560 device contains a function with which updates
to multiple devices can be synchronized using the
LOAD
function. There is not a dedicated pin available for this
function; however, either the CLEN or
HW_INH
pin can
be used as a
LOAD
input (selection is made in the system
control register, Address 0x1, Bits[8:7]).
When selected as the
LOAD
function, the pin no longer
operates in its previous function (power-on default for each
of these pins is a CLEN or
HW_INH
function).
The
LOAD
function controls the following registers:
• 0x8 FIN DAC x2 register
• 0xD CLL DAC x2 register
• 0x10 CLH DAC x2 register
• 0x4 Compensation Register 1
• 0x5 Compensation Register2
• 0x2 DPS Register1 (only current ranges, Bits[13:11])
There is, however, an alternate method for updating and using
the CLEN and
HW_INH
pins in their normal function.