Datasheet

Data Sheet AD5560
Rev. D | Page 19 of 68
Pin No. Mnemonic Description
D1
TMPALM
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched
or unlatched.
D2 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO).
D3 CPOL Comparator Low Output.
D7 EXTMEASIH2 Input High Measure Line for External High Current Range 2.
D8 EXTMEASIH1 Input High Measure Line for External High Current Range 1.
D9,H3, J8 AV
DD
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
E1
BUSY
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
E2 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
E3 DV
CC
Digital Supply Voltage.
E7
GUARD/SYS_DUTGND
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
E8 AGND Analog Ground.
E9, G4, J4
AV
SS
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
F1 DGND Digital Ground Reference Point.
F2 SCLK Clock Input, Active Falling Edge.
F3 SDI Serial Data Input.
F7
SENSE
Input Sense Line.
F8 EXTMEASIL Low Side Measure Current Line for External High Current Ranges.
F9 DUTGND Device Under Test Ground.
G1
SYNC
Frame Sync, Active Low.
G2 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied
to this input to drive the ramp circuitry. Tie RCLK low if it is unused.
G3
RESET
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
G5 C
C0
Compensation Capacitor Input 0.
G6 SYS_SENSE External Sense Signal Output.
G7 SYS_FORCE External Force Signal Input.
G8 C
F2
Feedforward Capacitor 2.
G9 C
F0
Feedforward Capacitor 0.
H1
CLEN/
LOAD
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a
LOAD
function to allow synchronization of multiple devices. Either CLEN or
HW_INH
can be chosen as
LOAD
input (see the system control register, Address 0x1).
H2 VREF Reference Input for DAC Channels, Input Range is 2 V to 5 V.
H4 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
H5 C
C1
Compensation Capacitor Input 1.
H6 MASTER_OUT Master Output When Ganging Multiple DPS Devices.
H7 SLAVE_IN Slave Input When Ganging Multiple DPS Devices.
H8 C
F3
Feedforward Capacitor 3.
H9
C
F1
Feedforward Capacitor 1.
J1
HW_INH
/
LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a
LOAD
function to allow
synchronization of multiple devices. Either CLEN or
HW_INH
can be chosen as a
LOAD
input (see the system
control register, Address 0x1).
J2 REFGND Accurate Ground Reference for Applied Voltage Reference.
J3
AGND
Analog Ground.
J5 C
C3
Compensation Capacitor Input 3.
J6 C
C2
Compensation Capacitor Input 2.
J7 FORCE Output Force Pin for Internal Current Ranges.
J9 C
F4
Feedforward Capacitor 4.