Datasheet

Data Sheet AD5560
Rev. D | Page 13 of 68
TIMING CHARACTERISTICS
HCAV
DD
x ≤ AV
SS
+ 33 V, HCAV
SS
x ≥ AV
SS
, AV
DD
≥ 8 V, AV
SS
5 V, |AV
DD
− AV
SS
| ≥ 16 V and ≤ 33 V, V
REF
= 5 V (T
J
= 25°C to 90°C,
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
Parameter
1, 2, 3
DV
CC
= 2.3 V
to 2.7 V
DV
CC
= 2.7 V
to 3.3 V
DV
CC
= 4.5 V
to 5.5 V Unit Description
t
UPDATE
600 600 600 ns max Channel update cycle time
t
1
25 20 20 ns min SCLK cycle time; 60/40 duty cycle
t
2
10 8 8 ns min SCLK high time
t
3
10 8 8 ns min SCLK low time
t
4
10 10 10 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
15 15 15 ns min Minimum
SYNC
high time
t
6
5 5 5 ns min 24
th
SCLK falling edge to
SYNC
rising edge
t
7
5
5
5
ns min
Data setup time
t
8
4.5 4.5 4.5 ns min Data hold time
t
9
4
40 35 30 ns max
SYNC
rising edge to
BUSY
falling edge
t
10
1.5 1.5 1.5 μs max
BUSY
pulse width low for DAC x1 write
280 280 280 ns max
BUSY
pulse width low for other register write
t
11
25 20 10 ns min
RESET
pulse width low
t
12
400 400 400 µs max
RESET
time indicated by
BUSY
low
t
13
250 250 250 ns min Minimum
SYNC
high time in readback mode
t
14
5, 6
45 35 25 ns max SCLK rising edge to SDO valid
t
15
30 30 30 ns max
SYNC
rising edge to SDO high-Z
LOAD
TIMING
t
16
20 20 20 ns min
LOAD
pulse width low
t
17
150 150 150 ns min
BUSY
rising edge to force output response time
t
18
0 0 0 ns min
BUSY
rising edge to
LOAD
falling edge
t
19
150 150 150 ns min
LOAD
rising edge to FORCE output response time
150
150
150
ns min
LOAD
rising edge to current range response
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit shown in Figure 2.
5
This is measured with the load circuit shown in Figure 3.
6
Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
TIMING DIAGRAMS
TO OUTPUT
PIN
DV
CC
R
LOAD
2.2kΩ
C
LOAD
50pF
V
OL
07779-002
Figure 2. Load Circuit for Open Drain
07779-003
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OL
TO OUTPUT
PIN
C
LOAD
50pF
Figure 3. Load Circuit for CMOS