Data Sheet 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs AD5560 FEATURES Programmable device power supply (DPS) FV, MI, MV, FNMV functions 5 internal current ranges (on-chip RSENSE) ±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA 2 external high current ranges (external RSENSE) EXTFORCE1: ±1.
AD5560 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Adjusting the Autocompensation Mode ................................. 39 Applications ....................................................................................... 1 Dealing with Parallel Load Capacitors .................................... 39 General Description ......................................................................... 1 DAC Levels ..
Data Sheet AD5560 REVISION HISTORY 8/12—Rev. C to Rev. D 12/08—Rev. 0 to Rev. A Added 72-Ball Flip-Chip BGA (Throughout) ............................... 1 Added Figure 7 and Table 5 (Renumbered Sequentially) ..........18 Added Applications Information Section ....................................62 Updated Outline Dimensions ........................................................64 Changes to Ordering Guide ...........................................................65 Changes to Figure 1 ..............
Figure 1. Rev. D | Page 4 of 68 VREF SW16 MEASOUT RESET GPO 16 16 16 OFFSET OFFSET 16-BIT DAC ISENSE VSENSE KSENSE TSENSE DUTGND SENSE DIAGNOSTIC A DIAGNOSTIC B ×2 REG ×2 REG 16-BIT DAC SDO SCLK SDI SYNC BUSY SERIAL SPI INTERFACE ×1/×0.
Data Sheet AD5560 SPECIFICATIONS HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC = 2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C, maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is full-scale current range. Table 1.
AD5560 Parameter Measure Current Ranges Data Sheet Min Typ Max Unit ±5 ±25 ±250 ±2.5 ±25 ±500 µA µA µA mA mA mA ±120 0 mA MEASURE CURRENT Differential Input Voltage Range1 Output Voltage Span1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Gain Error Gain Error1 Gain Error Tempco1 MEASOUT Gain = 1 Linearity Error MEASOUT Gain = 0.2 Linearity Error Linearity Error MEASOUT Gain = 0.
Data Sheet Parameter MEASOUT Gain = 0.2 Linearity Error Offset Error Offset Error Tempco1 AD5560 Min Max Unit Test Conditions/Comments −5.5 +5.5 mV −9 +24 mV −4 +13 mV +20 10 mV µV/°C 50 nV/√Hz Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC). Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC). Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC). Referred to MV output. Standard deviation = 12 µV/°C, referred to MV output.
AD5560 Parameter SYS_FORCE Voltage Range Current Carrying Capability1 Leakage Current Leakage Current Tempco1 Path On Resistance Pin Capacitance1 SYS_DUTGND Voltage Range Path On Resistance CURRENT CLAMP Clamp Accuracy Data Sheet Min Typ AVSS −25 −2.5 ±0.00 5 Max Unit AVDD +25 +2.5 ±0.
Data Sheet Parameter SETTLING TIME (FV, MEASURE CURRENT) MI (1200 mA EXTFORCE1 Range)1 MI (900 mA EXTFORCE1 Range)1 MI (500 mA EXTFORCE2 Range)1 AD5560 Min Typ Max Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) 30 40 32 42 69 95 Unit Test Conditions/Comments To within 10 mV of programmed value. µs µs µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load. 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load. 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load.
AD5560 Parameter Comparator DAC Dynamic Output Voltage Settling Time1 Slew Rate1 Digital-to-Analog Glitch Energy1 Glitch Impulse Peak Amplitude1 REFERENCE INPUT VREF DC Input Impedance VREF Input Current VREF Range1 COMPARATOR Error VOLTAGE COMPARATOR Propagation Delay1 Error1 CURRENT COMPARATOR Propagation Delay1 Error1 MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 Measure Output Voltage Span1 Measure Output Voltage Span1 Measure Output Voltage Span1 Measure Pin Output Impedance Output Leakage Curre
Data Sheet Parameter SPI INTERFACE LOGIC Logic Inputs Input High Voltage, VIH AD5560 Min Typ Max 1.7/2.0 Input Low Voltage, VIL Unit Test Conditions/Comments V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels. (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels. 0.7/0.8 V +1 10 µA pF 0.4 +1 10 V V μA pF 0.4 10 V pF 4 28 V HCAVSS1x HCAVDD2x −25 4 −5 28 V V HCAVSS2x AVDD AVSS DVCC AIDD 4 AISS4 DICC AIDD4 −25 8 −25 2.3 −5 28 −5 5.
AD5560 Parameter Power Supply Sensitivity1 ΔForced Voltage/ΔAVDD ΔForced Voltage/ΔAVSS ΔForced Voltage/ΔHCAVDDx ΔForced Voltage/ΔHCAVSSx ΔMeasured Current/ΔAVDD ΔMeasured Current/ΔAVSS ΔMeasured Current/ΔHCAVDDx ΔMeasured Current/ΔHCAVSSx ΔMeasured Voltage/ΔAVDD ΔMeasured Voltage/ΔAVSS ΔMeasured Voltage/ΔHCAVDDx ΔMeasured Voltage/ΔHCAVSSx ΔForced Voltage/ΔDVCC ΔMeasured Current/ΔDVCC ΔMeasured Voltage/ΔDVCC Data Sheet Min Typ Max −65 −65 −90 −90 −50 −43 −90 −90 −65 −65 −90 −90 −80 −80 −80 Unit dB dB dB
Data Sheet AD5560 TIMING CHARACTERISTICS HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C, maximum specifications, unless otherwise noted). Table 2. SPI Interface Parameter 1, 2, 3 tUPDATE t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t10 t11 t12 t13 t14 5, 6 t15 LOAD TIMING t16 t17 t18 t19 DVCC = 2.3 V to 2.7 V 600 25 10 10 10 15 5 5 4.5 40 1.5 280 25 400 250 45 30 DVCC = 2.7 V to 3.3 V 600 20 8 8 10 15 5 5 4.5 35 1.
AD5560 Data Sheet t1 SCLK 1 24 2 t2 t3 t4 t6 SYNC t5 t7 t8 DB0 DB23 SDI t9 t10 BUSY t16 LOAD1,3 FORCE EXTFORCE1 EXTFORCE21 t17 t18 t16 LOAD2,3 FORCE EXTFORCE1 EXTFORCE22,3 t19 t11 RESET t12 1LOAD ACTIVE DURING BUSY. 2LOAD ACTIVE AFTER BUSY. 3LOAD FUNCTION IS AVAILABLE 07779-004 BUSY VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2. Figure 4.
Data Sheet AD5560 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AVSS AVDD to AGND AVSS to AGND HCAVDDx to HCAVSSx HCAVDDx to AGND HCAVSSx to AGND HCAVDDx to AVSS HCAVDDx to AVDD HCAVSSx to AVSS DVCC to DGND AGND to DGND REFGND to AGND Digital Inputs to DGND Analog Inputs to AGND EXTFORCE1 and EXTFORCE2 to AGND1 Storage Temperature Operating Junction Temperature Reflow Profile Junction Temperature Power Dissipation ESD HBM FICDM 1 Rating 34 V −0.3 V to +34 V −34 V to +0.3 V 34 V −0.
AD5560 Data Sheet EXTFORCE1A HCAV DD1A HCAV SS2A HCAV SS1A EXTFORCE2A HCAV DD2A HCAV DD1B EXTFORCE1B HCAV SS2B HCAV SS1B EXTFORCE2B HCAV DD2B HCAV DD1C EXTFORCE1C HC_V SS1C GPO PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 EXTMEASIH2 47 EXTMEASIH1 TMPALM 3 46 AVDD CPOH/CPO 4 45 AVSS CPOL 5 44 AGND BUSY 6 43 GUARD/SYS_DUTGND 42 EXTMEASIL 41 SENSE 40 DUTGND 39 CF0 SDI 11 38 CF1 SYNC 12 37 CF2 RCLK 13 36 CF3 RE
Data Sheet Pin No.
Data Sheet 9 8 7 6 5 4 3 2 1 A EXTFORCE1A EXTFORCE1A EXTFORCE2A EXTFORCE1B EXTFORCE1B EXTFORCE2B EXTFORCE1C EXTFORCE1C GPO B HCAV DD1A HCAV SS1A HCAV DD2A HCAV DD1B HCAV SS1B HCAV DD2B HCAV DD1C HCAV SS1C CLALM C HCAVDD1A HCAVSS1A HCAVSS2A HCAVDD1B HCAVSS1B HCAVSS2B HCAVDD1C HCAVSS1C KELALM D AVDD EXTMEASIH1 EXTMEASIH2 CPOL CPOH/CPO TMPALM E AVSS AGND GUARD/ SYS_DUTGND DVCC SDO BUSY F DUTGND EXTMEASIL SENSE SDI SCLK DGND G CF0 CF2 SYS_FORCE SYS
Data Sheet Pin No. D1 Mnemonic TMPALM D2 D3 D7 D8 D9,H3, J8 CPOH/CPO CPOL EXTMEASIH2 EXTMEASIH1 AVDD E1 E2 BUSY SDO E3 E7 DVCC GUARD/SYS_DUTGND E8 E9, G4, J4 AGND AVSS F1 F2 F3 F7 F8 F9 G1 G2 DGND SCLK SDI SENSE EXTMEASIL DUTGND SYNC RCLK G3 G5 G6 G7 G8 G9 H1 RESET CC0 SYS_SENSE SYS_FORCE CF2 CF0 CLEN/LOAD H2 H4 H5 H6 H7 H8 H9 J1 VREF MEASOUT CC1 MASTER_OUT SLAVE_IN CF3 CF1 HW_INH/LOAD J2 J3 J5 J6 J7 J9 REFGND AGND CC3 CC2 FORCE CF4 AD5560 Description Temperature Alarm Flag.
AD5560 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.2 12 1.0 10 8 MV LINEARITY (mV) 0.6 0.4 0.2 6 MEASOUT GAIN = 0.2 4 2 0 MEASOUT GAIN = 1 –2 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE –4 07779-026 –0.2 0 10,000 20,000 30,000 40,000 Figure 8. Force Voltage Linearity vs. Code, VREF = 5 V, No Load 60,000 Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1, MEASOUT Gain = 0.2, Negative Skew Supply) 2.0 0.0100 TJ = 25°C AVDD = 16.25V AVSS = –16.
Data Sheet 0.0500 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V ±25mA RANGE 0.0375 AVDD = +16.25V AVSS = –16.25V 0.0375 V REF = 5V OFFSET DAC = 0x8000 0.0250 MI GAIN = 20 MEASOUT GAIN = 0.2 NOMINAL SUPPLIES 0.0125 LINEARITY (%) LOW SUPPLIES 0 –0.0125 –0.0375 0 –0.0125 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE Figure 14. Measure Current Linearity vs.
AD5560 Data Sheet 0 0.15 EXTFORCE1A EXTFORCE2B EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE 0.05 0 TJ = 25°C –0.02 –0.04 GAIN ERROR (%) LEAKAGE CURRENT (nA) 0.10 –0.05 HIGH NOMINAL –0.06 LOW –0.08 –0.10 –0.10 –0.15 5 10 STRESS VOLTAGE (V) 25 35 45 55 0 AV DD = ±16.25V AV SS = –16.25V VREF = 5V OFFSET DAC = 0x8000 VSTRESS = 9V 1.6 0.
Data Sheet AD5560 0 5 HIGH 4 –0.001 3 –0.003 LOW NOMINAL 2 OFFSET ERROR (mV) GAIN ERROR (%) –0.002 –0.004 –0.005 1 0 NOMINAL –1 –2 HIGH –3 LOW –0.006 35 45 55 65 75 85 TEMPERATURE (°C) –5 25 07779-045 –0.007 25 35 45 55 65 75 07779-044 –4 85 TEMPERATURE (°C) Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1 Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2 1.0 CH1 p-p 27mV CH1 AREA 10.92µVs 0.9 HIGH 0.8 OFFSET ERROR (mV) NOMINAL 0.7 LOW 0.
AD5560 Data Sheet CH1 p-p 159mV CH1 AREA 14.31µVs CH1 p-p 84mV TRIGGER 2 FORCE FORCE 1 1 3 CH1 50mV CH3 5V M200µs T 10.4% B W B W A CH3 07779-020 07779-017 SYNC 1.5V CH1 100mV B W CH2 5V M40µs T 120.4µs A CH2 1.6V Figure 35. Autocompensation Mode 90% to 10% ILOAD Change, EXTFORCE2 Range, 10 µF Load Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode, 25 mA ILOAD, 10 μF Load CH1 p-p 36mV CH1 AREA –9.
Data Sheet AD5560 CH1 p-p 174mV TRIGGER FORCE MEASOUT – MI 2 FORCE 1 2 07779-023 BUSY B CH1 100mV CH2 5V W M40µs T 120.4µs A CH2 07779-055 1 TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = 25mA 0 TO 10V STEP RLOAD = 40kΩ CLOAD = 220nF AUTOCOMP MODE 0x4480 MEASOUT GAIN 1, MI GAIN 20 4 3 4.6V CH1 5V CH3 5V Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 µF Load CH2 2V BW CH4 10V M20µs T 1.4% A CH3 2.9V Figure 41.
AD5560 Data Sheet 1000 PART H1 PART H2 PART H3 900 800 700 NSD (nV/√Hz) MEASOUT – MI TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = EXTFORCE1/1.2A 0 TO 3.7V STEP CLOAD = 10µF CERAMIC SAFE MODE MEASOUT GAIN 1, MI GAIN 20 200 FORCE 100 Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode 07779-025 GAIN = 11 GAIN = 10 FVMI GAIN = 01 2.9V FNMV GAIN = 00 A CH3 FVMV GAIN = 10 M20µs T 4.
Data Sheet AD5560 0 0 MI: GAIN 0 –20 –20 FOH MI: GAIN 0 –40 ACPSRR (dB) ACPSRR (dB) –40 –60 MV: GAIN 0 –60 MV: GAIN 0 –80 –80 –100 –100 –120 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –140 10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 50. ACPSRR of DVCC vs. Frequency Figure 52. ACPSRR of HCAVSSx vs. Frequency 1600 0 MI: GAIN 0 1400 –20 CABLE L = CABLE L = CABLE L = CABLE L = 2µH, CLAMP AT 1.2A 1µH, CLAMP AT 1.2A 0.2µH, CLAMP AT 1.2A 0µH, CLAMP AT 1.
AD5560 Data Sheet TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range (%FSR). Gain Error Gain error is the difference between full-scale error and zeroscale error. It is expressed in percentage of full-scale range (%FSR).
Data Sheet AD5560 THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic test equipment. All the DAC levels required to operate the device are available on chip. This block performs three functions related to the force and sense lines. • This device contains programmable modes to force a pin voltage and measure the corresponding current (FVMI) covering a wide current measure range of up to ±1.2 A.
AD5560 Data Sheet GPO The GPO pin can be used as an extra control bit for external switching functions, such as for switching out DUT decoupling when making low current measurements. The GPO pin is also internally connected to an array of thermal diodes scattered across the AD5560. The diagnostic register (Address 0x7) details the addressing and location of the diodes.
Data Sheet AD5560 resistors to further optimize stability and settling time performance. The AD5560 has three compensation modes: safe mode, autocompensation mode, and manual compensation mode, all of which are described in more detail in the Force Amplifier Stability section. HIGH CURRENT RANGES The range of suggested compensation capacitors allows optimum performance for any capacitive load from 0 pF to 160 μF using one of the modes previously listed.
AD5560 Data Sheet Master in FV Mode, Slaves in Force Current (FI) Mode The master device is placed into FV mode, and all slave devices into force current (FI) mode. The measured current of the master device (MASTER_OUT) is applied to the input of all slave devices (SLAVE_IN), and the slaves act as followers. All channels work to share the current equally among all devices in the gang. Because the slaves force current, matching the DUT paths is not so critical.
Data Sheet AD5560 DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN These diodes can be muxed out onto the GPO pin. The diagnostic register (Address 0x7) details the addressing and location of the diodes. These can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many AD5560 devices. When selected, the anode of each diode is connected to GPO and the cathode to AGND.
AD5560 Data Sheet VMIN is another inportant voltage level that is used in other parts of the circuit. When using a MEASOUT gain of 0.2, the VMIN level is used to scale the voltage range; therefore, when choosing supply rails, it is very important to ensure that there is sufficient footroom so that the VMIN level is not impinged on (the high voltage DAC amplifiers used here require approximately 2 V footroom to AVSS). See the Choosing AVDD/AVSS Power Supply Rails section for more information. VMIN = −5.
Data Sheet AD5560 VREF VMID = (VTOP – VBOT)/2 VMID VTOP R 8.25R 2R HV DAC AMP LOW VOLTAGE OFFSET DAC DAC att VOS = (1 + 2/8.25) × (OFFSET DAC VOLTAGE) 8.25R 2R 2R 8.25R R VBOT VMIN 5R att REFGND MEASOUT OSD DAC IN R INTERNAL MEASI LOW INTERNAL MEASI HIGH 10R tri MI_x10 MEASURE CURRENT ISENSE AMP 5R 1kΩ MI_x20 mi mi_gain R 10R 2R att 2R 5R MEASURE VOLTAGE 1kΩ mv att att 5R 5R 5R 5R 5R DUTGND VSENSE AMP SENSE NOTES 1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.
AD5560 Data Sheet FORCE AMPLIFIER STABILITY Table 12. External Variables There are three modes for configuring the force amplifier: safe mode, autocompensation mode, and manual compensation mode. Manual compensation mode has highest priority, followed by safe mode, then autocompensation mode. Name CR RC CD RD IR Safe Mode Selected through Compensation Register 1 (see Table 20), this mode guarantees stability of the force amplifier under all conditions.
Data Sheet AD5560 POLES AND ZEROS IN A TYPICAL SYSTEM Typical closed loop systems have one dominant pole in the feedback path, providing −20 dB/decade gain roll off and 90° of phase shift so that the gain decreases to 0 dB where there is a conservative 90° of phase margin. The AD5560 has compensation options to help cope with the various load conditions that a DPS is presented with.
AD5560 Data Sheet stability problems. This is most likely to be the case when there are both a large CR and large RC. settings when using the manual compensation register (this algorithm is what the autocompensation method is based upon): The RP resistor is intended to solve this problem. Again, it is prudent not to cancel exact pole/zero cancellation with RZ and instead allow the zero to be 2× to 3× the frequency of the pole. It is best to be very conservative when using RZ to cancel the load pole.
Data Sheet AD5560 10. Calculate FZ, the ESR zero frequency, using FZ = 1/(2πRcCr). 11. If FP > Fug, the load pole is above the bandwidth of the AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the algorithm 12. If RC < (R0/25), then the ESR is negligible. Attempt to cancel the load pole with RZ zero. Choose an ideal zero frequency of 2 × FP for some safety margin and then choose the RZ[2:0] value that gives the closest frequency on a logarithmic scale. This ends the algorithm 13.
AD5560 Data Sheet Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V The transfer function for these 16-bit DACs is DAC CODE VCLH , VCLL = 5.125 × VREF × − 5.125 × VREF × 216 OFFSET _ DAC _ CODE + DUTGND 216 The transfer function for the clamp current value is DAC CODE − 32768 5.125 × VREF × 216 ICLL, ICLH = RSENSE × MI _ AMP _ GAIN where: RSENSE is the sense resistor. MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
Data Sheet AD5560 REFERENCE SELECTION The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs and the current ranges. This device can be used with a reference input ranging from 2 V to 5 V. However, for most applications, a reference input of 5 V is able to meet all voltage range requirements. The DAC amplifier gain is 5.125, which gives a DAC output span of 25.625 V.
AD5560 Data Sheet PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE The exposed pad and leads of the TQFP package have a 100% tin finish. The exposed paddle is connected internally to AVSS. The simulated maximum allowable force for a single lead is 0.18 lbs; total allowable force for the package is 11.5 lbs. The quoted maximum force may cause permanent lead bending. Other package failure (die, mold, board) may occur first at lower forces.
Data Sheet AD5560 NEW RAMP CHANGE STEP SIZE? YES SELECT RAMP SIZE NO CHANGE CLOCK DIVISION? YES PROGRAM CLOCK DIVIDER YES WRITE NEW FIN ×1 DAC VALUE NO CHANGE RAM P START? NO WRITE RAMP END CODE RAMP MODE ENABLE RAMP UPDATE DAC CODE? YES CALCULATE NEXT DAC CODE LOAD DAC NO INTERRUPT RAMP? ALARM? YES DO NOT LOAD DAC. RETAIN PREVIOUS VALUE NO RAMP COMPLETE? YES RETURN TO NORMAL MODE TERMINATE RAMP Figure 58. Flow Chart for Ramp Function Rev.
AD5560 Data Sheet SERIAL INTERFACE The AD5560 contains an SPI-compatible interface operating at clock frequencies of up to 50 MHz. To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. SPI INTERFACE The serial interface is 2.5 V LVTTL-compatible when operating from a 2.3 V to 3.6 V DVCC supply.
Data Sheet AD5560 If Bits[8:7] of the system control register (Address 0x1) are high, then the CLEN and HW_INH operate as normal, and the update waits until BUSY goes high (this way multiple channels can still be synchronized by simply tying BUSY pins together). REGISTER UPDATE RATES As mentioned previously, the value of the x2 register is calculated each time the user writes new data to the corresponding x1 register. The calculation is performed by a three stage process.
AD5560 Data Sheet CONTROL REGISTERS DPS AND DAC ADDRESSING A no operation (NOP) command performs no function within the device. This code may be useful when performing a readback function where a change of DAC or DPS register is not required. The serial word assignment consists of 24 bits, as shown in Table 16. All write-to registers can be read back. There are some read-only registers (Address 0x43 and Address 0x44). DAC x2 registers are not available for readback. Table 16.
Data Sheet AD5560 Table 18. DPS Register 1 Address 0x2 Default 0x0000 Bit 15 Name SW-INH Data Bits, MSB First Function This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the HW_INH hardware inhibit pin. 14 13 12 11 Reserved I[2:0] Reserved, set to 0. Current range addressing. These bits allow selection of the required current range. 10 CMP[1:0] 9 8 7 6 5 ME[3:0] 4 CLEN 3:0 Unused I Action 0 ±5 µA current range.
AD5560 Data Sheet Table 19. DPS Register 2 Address 0x3 Default 0x0000 Bit 15 Name SF0 14 13 12 SR[2:0] 11 GPO 10 9 SLAVE, GANGIMODE 8 INT10K 7 Guard high-Z 6:0 Unused Data Bits, MSB First Function System force and sense line addressing, SF0. Bit SF0 addresses each of the different combinations of switching the system force and sense lines to the force and sense pins at the DUT.
Data Sheet AD5560 The AD5560 has three compensation modes. The power-on default mode is SAFEMODE enabled. This ensures that the device is stable into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions. Table 20.
AD5560 Data Sheet Table 21. Compensation Register 2 Address 0x5 Default 0x0110 Bit 15 Name Manual compensation 14 13 12 RZ[2:0] 11 10 9 RP[2:0] 8 7 gm[1:0] Data Bits, MSB First Function The AD5560 can be manually configured to compensate the force amplifier into a wide range of load conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of Compensation Register 1.
Data Sheet AD5560 Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer flags on the appropriate open-drain pin; however, the alarm status is still available in both of the alarm status registers (Address 0x43 and Address 0x44). Table 22.
AD5560 Data Sheet Table 23. Diagnostic Register Address 0x7 Default 0x0000 Bit 15 14 13 12 Name DIAG select[3:0] 11 10 9 8 7 TSENSE select[3:0] Data Bits, MSB First Function DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT.
Data Sheet Address 0x7 Default 0x0000 AD5560 Data Bits, MSB First Bit Name 6 5 Test Force AMP[1:0] 4:0 Reserved Function 24 25 26 Force amplifier NPNs 1A-1 1A-2 2A (similar location to VPTAT high for EXTFORCE2 range) 1B-1 (similar location to VPTAT high for EXTFORCE1 27 range) 28 1B-2 29 2B 30 1C-1 31 1C-2 These register bits allow disabling of stages of the force amplifier. They can be used to ensure connectivity in each parallel stage.
AD5560 Data Sheet Table 24.
Data Sheet AD5560 Address 0x3C 0x3D 0x3E Register CPH DAC c EXT Range 1 DGS DAC Ramp end code Default 0x8000 0x3333 0x0000 0x3F Ramp step size 0x0001 0x40 RCLK divider 0x0001 0x41 0x42 Enable ramp Interrupt ramp 0x0000 0x0000 Data Bits, MSB First D15 to D0. D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range. D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN DAC register. 0000 0000 D6 to D0.
AD5560 Data Sheet Table 25. Alarm Status and Clear Alarm Status Register Address 0x43 Register Alarm status Default 0x0000 0x44 Alarm status and clear alarm 0x0000 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B to 0x7F CPL DAC x1 CPL DAC m CPL DAC c CPH DAC x1 CPH DAC m CPH DAC c Reserved 0x0000 0xFFFF 0x8000 0xFFFF 0xFFFF 0x8000 Data Bits, MSB first This register is a read-only register providing information on the status of the alarm functions and the comparator outputs.
Data Sheet AD5560 READBACK MODE DAC READBACK The AD5560 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the DAC register (x2 calibrated register). To read back contents of a register, it is necessary to write a 1 to the R/W bit, address the appropriate register, and fill the data bits with all zeros. The DAC x1, DAC m, and DAC c registers are available to read back via the serial interface.
AD5560 Data Sheet Table 26.
Data Sheet AD5560 USING THE HCAVDDx AND HCAVSSx SUPPLIES internal pull-up resistors between the supplies (see Figure 59). Using diodes here allows a more flexible use of supplies and can minimize the amount of supply switching required. In the example, the AVDD and AVSS supplies can support the high voltage needs, whereas the HCAVDDx and HCAVSSx supplies support the low voltage, higher current ranges. Diode selection should take into account the current carrying requirements.
AD5560 Data Sheet five feedforward capacitor input pins, all capacitor inputs may be used only if the user intends to drive large variations of DUT load capacitances. If the DUT load capacitance is known and doesn’t change for all combinations of voltage ranges and test conditions, then it is possible only one set of CCx and CFx is required. REQUIRED EXTERNAL COMPONENTS The minimum required external components are shown in the block diagram in Figure 60.
Data Sheet AD5560 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5560 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5560 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only.
AD5560 Data Sheet APPLICATIONS INFORMATION THERMAL CONSIDERATIONS Table 28. Thermal Resistance for TQFP_EP1 Cooling No Heat Sink Heat Sink7 Cold Plate8 Airflow (LFPM) 0 200 500 0 200 500 N/A θJA2 39 37.2 35.7 12.2 11.1 9.5 N/A θJC (Uniform)3 θJC (Local)4 Ideal TIM6 θJC (Local) w/TIM6 1.0 2.8 4.91 1.0 2.8 4.91 θJCP w/TIM5 N/A N/A 7.5 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 1 All numbers are simulated and assume a JEDEC 4-layer test board.
Data Sheet AD5560 TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE BGA Package Due to localized heating, temperature at the top surface of the package has steep gradient. Thus, the θJC value is highly dependent on where the case temperature is measured. Figure 61 shows the top of the die temperature contour map for the TQFP_EP. Due to localized heating, temperature at the top surface of the package has steep gradient. Thus, the θJC value is highly dependent on where the case temperature is measured.
AD5560 Data Sheet OUTLINE DIMENSIONS 1.20 MAX 0.75 0.60 0.45 12.20 12.00 SQ 11.80 0.675 0.872 5.95 BSC 64 49 1 1.00 REF 49 48 64 1 48 SEATING PLANE EXPOSED PAD 5.95 BSC 10.20 10.00 SQ 9.80 7.85 BSC TOP VIEW (PINS DOWN) 0.15 0.05 0.08 COPLANARITY BOTTOM VIEW 16 0.20 0.09 33 17 7° 3.5° 0° VIEW A 32 16 17 32 7.85 BSC 0.27 0.22 0.17 0.50 BSC LEAD PITCH FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Data Sheet AD5560 ORDERING GUIDE Model 1 AD5560JSVUZ AD5560JSVUZ-REEL AD5560JBCZ AD5560JBCZ-REEL EVAL-AD5560EBUZ 1 2 Temperature Range 2 TJ = 25°C to +90oC TJ = 25°C to +90oC TJ = 25°C to +90oC TJ = 25°C to +90oC Package Description 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) 72-Ball Chip Scale Package Ball Grid Array (CSP-BGA) 72-Ball Chip Scale Package Ball Grid Array (CSP-BGA) Evaluation Kit Z = RoHS Compliant Part.
AD5560 Data Sheet NOTES Rev.
Data Sheet AD5560 NOTES Rev.
AD5560 Data Sheet NOTES ©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07779-0-8/12(D) Rev.
