Datasheet

Data Sheet AD5522
Rev. E | Page 13 of 64
Circuit and Timing Diagrams
TO
OUTPUT
PIN
DVCC
R
LOAD
2.2kΩ
C
LOAD
50pF
V
OL
06197-003
Figure 3. Load Circuit for
CGALM
,
TMPALM
06197-004
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OH
TO OUTPUT
PIN
C
LOAD
50pF
Figure 4. Load Circuit for SDO,
BUSY
Timing Diagram
SYNC
SCLK
SDI
BUSY
RESET
1 1
2
t
3
t
2
29
t
4
t
6
t
5
t
1
t
7
t
8
t
9
DB28
(N)
DB0
(N)
DB28
(N+1)
DB0
(N + 1)
29
t
10
t
16
t
17
BUSY
1
LOAD ACTIVE DURING BUSY.
2
LOAD ACTIVE AFTER BUSY.
LOAD
1
FOHx
1
LOAD
2
FOHx
2
t
11
t
12
t
13
t
14
t
12
t
15
06197-005
Figure 5. SPI Write Timing (Write Word Contains 29 Bits)