Datasheet

AD5522 Data Sheet
Rev. E | Page 12 of 64
Parameter
1, 2, 3
DVCC, Limit at T
MIN
, T
MAX
Unit Description
2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V
t
16
1.8 1.2 0.9 µs min
RESET
pulse width low
t
17
670 700 750 µs max
RESET
time indicated by
BUSY
low
t
18
400 400 400 ns min Minimum
SYNC
high time in readback mode
t
19
5, 6
60 45 25 ns max SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 5 and Figure 6.
4
Writes to more than one X1 register engages the calibration engine for longer times, shown by the
BUSY
low time, t
10
. Subsequent writes to one or more X1 registers
should either be timed or should wait until
BUSY
returns high (see Figure 56). This is required to ensure that data is not lost or overwritten.
5
t
19
is measured with the load circuit shown in Figure 4.
6
SDO output slows with lower DVCC supply and may require use of a slower SCLK.
Table 3. LVDS Interface
DVCC, Limit at T
MIN
, T
MAX
Parameter
1, 2, 3
2.7 V to 3.6 V 4.5 V to 5.25 V Unit Description
t
1
20 12 ns min SCLK cycle time
t
2
8 5 ns min SCLK pulse width high and low time
t
3
3
3
ns min
SYNC
to SCLK setup time
t
4
3 3 ns min Data setup time
t
5
5 3 ns min Data hold time
t
6
3 3 ns min SCLK to
SYNC
hold time
t
7
4
45 25 ns min SCLK rising edge to SDO valid
t
8
150 150 ns min Minimum
SYNC
high time in write mode after
X1 register write
70 70 ns min Minimum
SYNC
high time in write mode after
any other register write
400 400 ns min Minimum
SYNC
high time in readback mode
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 7.
4
SDO output slows with lower DVCC supply and may require use of slower SCLK.