Datasheet

Data Sheet AD5522
Rev. E | Page 11 of 64
Parameter Min Typ
1
Max Unit Test Conditions/Comments
Power Supply Sensitivity
2
From dc to 1 kHz
ΔForced Voltage/ΔAVDD −80 dB
ΔForced Voltage/ΔAVSS −80 dB
ΔMeasured Current/ΔAVDD −85 dB
ΔMeasured Current/ΔAVSS −75 dB
ΔForced Current/ΔAVDD −75 dB
ΔForced Current/ΔAVSS −75 dB
ΔMeasured Voltage/ΔAVDD −85 dB
ΔMeasured Voltage/ΔAVSS −80 dB
ΔForced Voltage/ΔDVCC −90 dB
ΔMeasured Current/ΔDVCC −90 dB
ΔForced Current/ΔDVCC −90 dB
ΔMeasured Voltage/ΔDVCC −90 dB
1
Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted.
2
Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted.
TIMING CHARACTERISTICS
AVDD ≥ 10 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 20 V and ≤ 33 V, DVCC = 2.3 V to 5.25 V, VREF = 5 V, T
J
= 25°C to 90°C, unless
otherwise noted.
Table 2. SPI Interface
Parameter
1, 2, 3
DVCC, Limit at T
MIN
, T
MAX
Unit Description
2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V
t
WRITE
4
1030 735 735 ns min Single channel update cycle time (X1 register write)
950 655 655 ns min Single channel update cycle time (any other register write)
t
1
30 20 20 ns min SCLK cycle time
t
2
8 8 8 ns min SCLK high time
t
3
8 8 8 ns min SCLK low time
t
4
10 10 10 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
4
150 150 150 ns min Minimum
SYNC
high time in write mode after X1 register
write (one channel)
70 70 70 ns min Minimum
SYNC
high time in write mode after any
other register write
t
6
10 5 5 ns min 29
th
SCLK falling edge to
SYNC
rising edge
t
7
5 5 5 ns min Data setup time
t
8
9 7 4.5 ns min Data hold time
t
9
120 75 55 ns max
SYNC
rising edge to
BUSY
falling edge
t
10
BUSY
pulse width low for X1 and some PMU register writes;
see Table 17 and Table 18
1 DAC X1 1.65 1.65 1.65 µs max
2 DAC X1 2.3 2.3 2.3 µs max
3 DAC X1 2.95 2.95 2.95 µs max
4 DAC X1 3.6 3.6 3.6 µs max
Other Registers 270 270 270 ns max System control register/PMU registers
t
11
20 20 20 ns min 29
th
SCLK falling edge to
LOAD
falling edge
t
12
20 20 20 ns min
LOAD
pulse width low
t
13
150
150
150
ns min
BUSY
rising edge to FOHx output response time
t
14
0 0 0 ns min
BUSY
rising edge to
LOAD
falling edge
t
15
100 100 100 ns max
LOAD
falling edge to FOHx output response time