Datasheet

Data Sheet AD5424/AD5433/AD5445
Rev. D | Page 9 of 28
03160-008
9
12
DB6 DB3
10
11
DB5 DB4
1
2
3
4
5
6
7
8
20
13
14
15
16
17
18
19
AD5445
(Not to Scale)
I
OUT
1
I
OUT
2
GND
DB11
DB10
DB9
DB8
DB7
R
FB
V
REF
V
DD
R/W
CS
DB0 (LSB)
DB1
DB2
Figure 7. AD5445 Pin Configuration (TSSOP)
03160-109
14
1
3
12
1
3
4
CS
15
R/W
DB0
DB1
11
DB2
GND
DB10
2
DB
1
1
DB9
5
DB8
7
DB6
6
DB7
8
DB5
9
DB4
10
DB3
19
I
OUT
1
20
I
OUT
2
18
R
FB
17
V
REF
16
V
DD
NOTES
1. THE EXPOSED P
AD MUST BE CONNECTED T
O
AGND.
AD5445
TO
P
VIEW
(Not to Scale)
Figure 8. AD5445 Pin Configuration (LFCSP)
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 I
OUT
1 DAC Current Output.
2 20 I
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3 1 GND Ground Pin.
4 to 15 2 to 13 DB11 to DB0 Parallel Data Bits 11 to 0.
16
14
CS
Chip Select Input. Active low. Used in conjunction with R/
W
to load parallel data to the input
latch or to read data from the DAC register. Rising edge of
CS
loads data.
17 15 R/
W
Read/Write. When low, use in conjunction with
CS
to load parallel data. When high, use with
CS
to read back contents of DAC register.
18 16 V
DD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
V
REF
DAC Reference Voltage Input Terminal.
20 18 R
FB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
Not applicable EPAD Exposed Pad. The exposed pad must be connected to AGND.