Datasheet

Evaluation Board User Guide UG-473
Rev. 0 | Page 15 of 20
DAUGHTER BOARD
J3-1
J3-2
J3-3
J3-4
J3-5
J4-1
J4-2
J4-3
J4-4
J4-5
J1-1
J1-2
J1-3 J1-4
J1-5
J1-6 J1-7
J1-8
J2-1
J2-2
J2-3
J2-4
J2-5
J2-6
J2-7 J2-8 J2-9
J2-10
J2-11
J2-12
ADDR0
ADDR1 SDA
SCL
SYNC SDO
SDI
SCLK
VDD
RESET
WP
LRDAC
DIS
INDEP
A1 W1 B1 A2
W2
B2
A3
W3
B3 A4
W4
B4
AGND
DGND
VLOGIC
VSS
VDD
VDD
9 10
8 14 6 12 11 7 13 1 5
VSS
C3
+
C4
A
W
B
A U1 AD5141 W B
2
3 4
16 15
LRDAC
LRDAC
VLOGIC
DIS
VSS
A1
A2
W1 W2
B1
A W B
B2
B2
W1
A1
OPAMP PROTECTION
A8
B
A
A7
B
A
A6
CIRCUIT CONNECTION
A– AMPLIFIER B– DAC + ATTENUATOR
B
A
ADDR1|SDO ADDR0|SYNC SDA|DIN RESET WP
VDD
VLOGIC
DIS
SDO|ADDR1
SYNC|ADDR0
DIN|SDA
SCLK|SCL
RESET
WP
GND
VSS
INDEP INDEP
0.1uF10uF
C2
VLOGIC
+
C1 0.1uF10uF
VLOGIC
GND VDD
U2
ADG774
DIS
DGND
15
EN
D4 D3 D2
D1
S4A S3A S4B S3B
S2A S1A S2B S1B
SYNC ADDR0 SDO
ADDR1 SDI SDA SCLK VLOGIC
INDEP DEPEN
VLOGIC
SCL
ADDR0|SYNC
12
9 7 4
13 14 10 11 6
5 3 2 16
ADDR1|SDO
SDA|DIN
SCL|SCLK
IN
1
DGND
DGND
DGND
VLOGIC
DGND
VLOGIC
DGND
DGND
ADDR0 ADDR1
INDEP
A2
I2C
SPI
B
A
A3
B
A
A4
B
A
A5
B
A
11010-016
Figure 17. Schematic of Daughter Board