Evaluation Board User Guide UG-046 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD1974 Four ADC with PLL 192 kHz, 24-Bit Codec EVAL-AD1974AZ PACKAGE CONTENTS interface board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC USB port and provides SPI access to the evaluation board through a ribbon cable.
UG-046 Evaluation Board User Guide TABLE OF CONTENTS EVAL-AD1974AZ Package Contents ............................................ 1 Powering the Board.......................................................................3 Other Supporting Documentation ................................................. 1 Setting Up the Master Clock (MCLK)........................................4 Evaluation Board Overview ............................................................ 1 Configuring the PLL Filter ........
Evaluation Board User Guide UG-046 SETTING UP THE EVALUATION BOARD STANDALONE MODE It is possible to run the board and the AD1974 ADC in standalone mode, which fixes the functionality of the AD1974 into the I2S data format, running at 256 × fS (default register condition). The ADC BCLK and LRCLK ports are flipped between slave and master (input and output) by tying COUT (Pin 24) to low or high.
UG-046 Evaluation Board User Guide C158 R166 R172 JP24 C170 R178 R156 08424-008 R156 C154 R155 R178 R175 EXT CLK IN JP30 HDR2 JP31 HDR1 08424-009 J23 U22 JP28 JP29 8416 R156 C154 R155 C153 R172 193X_MCLKO MCLKO BUS R166 JP24 R169 JP27 MCLKI BUS C168 R167 EXT CLK J23 U18 J22 Y1 JP23 CPLD U21 JP25 HDR2 OSC DISABLE HDR1 R178 R174 OSC C158 08424-007 MCLKI BUS L7 U22 JP28 EXT CLK JP20 MCLKO C147 XTAL R174 C168 C170 R175 EXT CLK IN 08424-010 R169 JP27 OSC DIS
Evaluation Board User Guide UG-046 JP15 C131 MCLK LRCLK C114 FILTER CM GND JP4 C89 C88 R107 C74 VREF SELECT TP32 C83 C82 R106 R76 C68 JP12 JP11 C77 R81 R79R77C62 R86 C76 S1 IN1L– TP28 R90 C72 C80 U14 C99 IN1R+ IN1R– TP34 Figure 13. VREF Selection and DC Coupling Jumpers Digital Audio 08424-012 JP15 C131 C75 IN1R PLL SELECT C120 C125 R138 R85 R87 Figure 11.
UG-046 Evaluation Board User Guide As an example, to set the ADC port as master, switch the ADC Control Register 2 bits for BCLK and LRCLK to master and change S2, Position 2, and S2, Position 5, to on. In this mode, the board is configured so that the ADC BCLK and LRCLK pins are the clock source for both the ADC destination and the DAC data source.
Figure 14. Settings Chart 1 Rev.
SPDIF_RX_8416 HDR1_DSDATA2 SPDIF_RX_8416 HDR1_DSDATA2 HDR1_DSDATA2 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA2 DAC_TDM_OUT DAC_TDM_OUT Aux ADC1 input TRISTATE SPDIF_RX_8416 SPDIF_RX_8416 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 TRISTATE Stereo Stereo Stereo Stereo Stereo N/A N/A Stereo/TDM Stereo Stereo TDM Dual- Line TDM DAC aux mode Stereo/TDM TRISTATE DAC_TDM_OUT Aux DAC2 output HDR1_DSDATA3 Aux ADC2 input TRISTATE
Evaluation Board User Guide UG-046 SCHEMATICS AND ARTWORK 08424-016 Figure 16. Board Schematics, Page 1—ADC Buffer Circuits Rev.
UG-046 Evaluation Board User Guide 08424-017 Figure 17. Board Schematics, Page 2—Serial Digital Audio Interface Headers with MCLK Direction Switching Rev.
Evaluation Board User Guide UG-046 08424-018 Figure 18. Board Schematics, Page 3—S/PDIF Receive and Transmit Interfaces Rev.
UG-046 Evaluation Board User Guide 08424-019 Figure 19. Board Schematics, Page 4—Serial Digital Audio Routing and Control CPLD Rev.
Evaluation Board User Guide UG-046 08424-020 Figure 20. Board Schematic, Page 5—AD1974 with MCLK Selection Jumpers Rev.
Evaluation Board User Guide 08424-021 UG-046 Figure 21. Board Schematics, Page 6—Daughter Card Interface, Useful as Test Points Rev.
Evaluation Board User Guide UG-046 08424-022 Figure 22. Board Schematics, Page 7—DAC Buffer Circuits Rev.
UG-046 Evaluation Board User Guide 08424-023 Figure 23. Board Schematics, Page 8—SPI Control Interface Rev.
UG-046 08424-024 Evaluation Board User Guide Figure 24. Board Schematics, Page 9—Power Supply Rev.
Evaluation Board User Guide 08424-025 UG-046 Figure 25. Top Assembly Layer Rev.
UG-046 08424-026 Evaluation Board User Guide Figure 26. Bottom Assembly Layer Rev.
UG-046 Evaluation Board User Guide CPLD CODE MODULE TITLE IF_Logic 'AD1974 EVB Input Interface Logic' //=================================================================================== // FILE: // REVISION DATE: AD1974_pld_revE.
Evaluation Board User Guide UG-046 BCLK_8416 pin 60 istype 'com'; LRCLK_8416 pin 59 istype 'com'; SOMS_RX,SFSEL1_RX,SFSEL0_RX,RMCKF_RX pin 66,67,64,65 istype 'com'; // S/PDIF Tx CS8404 pins SDATA_8406 'com'; pin 50 istype BCLK_8406,LRCLK_8406 pin 53, 54 istype 'com'; MCLK_8406 'com'; pin 49 istype APMS_TX,SFMT1_TX,SFMT0_TX pin 55,56,58 istype 'com'; CPLD_MCLK 'com'; pin 89 istype // AD1974 SPI port pins //CCLK,CDATA,CLATCH pin 84, 83, 85 istype 'com'; //COUT pin 82 istype 'com'; //CLATC
UG-046 Evaluation Board User Guide //================================================================================ "MACROS // Switch S3, DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL = ( MODE22 & MODE23); ADC_HDR_DATA2_DATA1 = ( MODE22 & !MODE23); ADC_HDR_TDM = (!MODE22 & MODE23); ADC_HDR_AUX = (!MODE22 & !MODE23); S/PDIF_OUT_MUX = MODE24; // HEX Switch S4 // S4 position 0, DAC_RX_ALL = ( MODE14 & MODE13 & MODE12 & MODE11); // S4 position 1, DAC_RX_1 = ( MODE14 & MODE13 & MODE12 & !MODE11); //
Evaluation Board User Guide UG-046 // S4 position B, DAC_DUAL_TDM = ( !MODE14 & MODE13 & DAC_HDR1_AUX = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // S4 position C, MODE12 & MODE11); // S4 position D, NA3 = ( !MODE14 & !MODE13 & MODE12 & !MODE11); // S4 position E, NA4 = ( !MODE14 & !MODE13 & !MODE12 & MODE11); // S4 position F, DAC_DATA_HIZ = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // Switch S2 DAC_S/PDIF = (DAC_CLK_SRC1 & DAC_CLK_SRC0); DAC_HDR1 = (DAC_CLK_SRC1 & !DAC_CLK_SRC0
UG-046 // Evaluation Board User Guide M3_8414 = 0; // CS8404 Tx interface mode select APMS_TX = 0; // Tx serial port is always slave in this application SFMT1_TX = 0; // Tx data format is I2S always SFMT0_TX = 1; // M0_8404 = 0; // M1_8404 = 0; // M2_8404 = 1; // I2S format only // divide 256Fs clock by 2 for 128Fs clock to the the S/PDIF Tx // Qdivide.clk = CPLD_MCLK; // Qdivide.
Evaluation Board User Guide UG-046 HDR1_DSDATA4.oe = (DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX); HDR1_ASDATA2.
UG-046 Evaluation Board User Guide ORDERING INFORMATION BILL OF MATERIALS Table 1.
Evaluation Board User Guide Qty 16 3 Designator R56, R57, R65, R66, R88, R89, R140, R154, R179, R183, R213, R216, R228 to R231 C25, C31, C45, C53, C169, C181, C190, C198 R3, R11, R58 1 C125 4 R5, R52, R53, R75 1 C120 33 R38 1 R129 8 3 C24, C34, C44, C56, C167, C185, C189, C201 C11, C14, C22, C26, C27, C30, C32, C35, C41, C46, C47, C52, C54, C57, C63, C66, C72, C75, C80, C105, C119, C133, C139, C148, C152, C164, C172, C179, C191, C196 C12, C18, C19 4 R83, R96, R148, R163 20 1 R103, R104,
UG-046 Evaluation Board User Guide Qty 1 Designator Y1 Description Crystal, 12.
Evaluation Board User Guide UG-046 Qty 1 Designator U10 Description 110 Ω AES/EBU transformer 2 1 2 2 1 1 U18, U22 U4 SW2, SW3 S2, S3 S6 U5 1 60 U7 TP1 to TP6, TP8 to TP10, TP12 to TP15, TP17, TP19 to TP23, TP25 to TP52, TP54 to TP60, TP62, TP64 to TP68 Buffer, three-state, single gate Octal, three-state buffer/driver SPDT slide switch PC mount 8-position SPST SMD switch, flush, actuated Tact switch, 6 mm gull wing 15 Mb/sec fiber optic receiving module with shutter Fiber optic transmit module, 15
UG-046 Evaluation Board User Guide NOTES Rev.
Evaluation Board User Guide UG-046 NOTES Rev.
UG-046 Evaluation Board User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
