Datasheet

Preliminary Technical Data EVAL-AD1940AZ
Rev. PrA | Page 7 of 30
USING THE EVALUATION BOARD
AD1940 SIGMADSP
The AD1940 is a complete 28-bit, single-chip, multi-channel
audio SigmaDSP
™ for equalization, multiband dynamic
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compen-
sate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940 is comparable to that
found in high end studio equipment. Most of the processing is
done in full, 56-bit double-precision mode, resulting in very
good, low level signal performance and the absence of limit
cycles or idle tones. The dynamics processor uses a
sophisticated, multiple-breakpoint algorithm often found in
high end broadcast compressors.
The AD1940 is a fully programmable DSP. Easy to use software
allows the user to graphically configure a custom signal
processing flow using blocks such as biquad filters, dyna-mics
processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1940’s digital input and output ports allow a glueless
connection to ADCs and DACs by multiple, 2-channel serial
data streams or TDM data streams. When in TDM mode, the
AD1940/AD1941 can input 8 or 16 channels of serial data, and
can output 8 or 16 channels of serial data. The input and output
port configurations can be individually set. The AD1940 is
controlled by a 4-wire SPI
® port.
The EVAL-AD1940AZ should be used to evaluate both the
AD1940 and the AD1941, which is equivalent to the AD1940
except for its I
2
C control interface.
POWER
The evaluation board uses two ADP3339 low-dropout voltage
reulators to generate the 3.3 V analog and digital supplies. The
current consumption of the board is approximately 500 mA at a
maximum.
The regulators’ inputs should be supplied with +5 to +6 V DC
power on connector J14. The power supply should have a
female cord plug with a 2.1 mm inner diameter, 5.5 mm outer
diameter, and 9.5 mm length. The polarization should be
positive-center.
A lab supply can also be used to power the board, and should be
connected across test points TP48 (VIN+) and TP70 (GND).
CLOCKING THE EVALUATION BOARD
The EVAL-AD1940AZ requires a master clock (MCLK) to
operate. The master clock can be supplied from a variety of
sources, and is used to clock the AD1940 DSP, AD1974 ADCs,
AD1939 ADCs/DACs, External Digital Audio Interfaces, and
the S/PDIF Transmitter.
In most common board configurations, MCLK will be
generated by the on-board AD1939. The AD1939 has an
internal oscillator that drives a 12.288 MHz crystal to produce a
12.288 MHz master clock suitable for 48 kHz, 96 kHz, and
192 kHz processing applications.
For configurations utilizing the S/PDIF receiver, MCLK must be
supplied to the system by the recovered MCLk of the S/PDIF
stream. This recovered MCLK has a frequency 256 times the
sample rate of the S/PDIF data.
A master clock can also be supplied from an external (off-
board) source on the digital audio interface headers J22, J23,
and J24. The corresponding MCLK direction switch should be
set to IN or OUT as required.
A description of the jumpers used to route MCLK is given in
Table 1. Examples of common MCLK configurations are given
in the Example Configurations section of this document and in
Figure 6.
Table 1. Master Clock Routing
Component Function
J1 Select MCLK Source/Destination
J3 Enable AD1939 Crystal Oscillator Circuit
SW3 Set direction of MCLK on H1 (J22)
SW4 Set direction of MCLK on H2 (J23)
SW5 Set direction of MCLK on H3 (J24)
J3
J1 J1J1J1
AD1939CRYSTAL
OSCILLATORMCLK
1939
XTAL
1939
RECOVERED
MCLKFROM
S/PDIFRX
DIR
EXTERNALMCLK
DIGITAL AUDIO
INTERFACEJ22
H1
AD1939CRYSTAL
OSCILLATORMCLK,
OUTPUTON
DIGITAL AUDIO
INTERFACEJ22
H1
J3
EXT
J3
EXT
J3
XTAL
SW3
OUT
SW3
OUT
SW3
IN
SW3
OUT
Figure 6. Example Master Clock Routing Settings
The AD1940 must be set up to properly receive MCLK as an
input to its PLL. The board will most often be used with a
12.288 MHz master clock, which is equivalent to 256×F
s
, with