Datasheet
Preliminary Technical Data EVAL-AD1940AZ
Rev. PrA | Page 15 of 30
BOARD SCHEMATICS
AD1940 SIGMADSP AND COMMUNICATIONS INTERFACE
Core Supply Regulation
Power Supply Bypass
Keep capacitors as close to the IC
as possible during board layout
Master Clock Source Selection
Pass Transistor beta>100
Power dissipation > 140 mW
3.3V to 2.5V
AD1940 SigmaDSP
AD1940 Serial Input Port:
AD1940 Inputs are always Slave
1940_D3V3
2.5V
AD1940 Mode Selection
USB_CLK
USBi Header
5V00_USB
MASTER_RESET
SCL
SDA
USB Control Interface
AD1940 Serial Output Port:
AD1940 Outputs can be Master or Slave
15
SDATA_IN1
11
BCLK_IN
8
PLL_VDD
14
SDATA_IN0
12
GND
17
SDATA_IN3
10
LRCLK_IN
43
INVDD
16
SDATA_IN2
41
SDATA_OUT6
45
VSENSE
9
NC
42
SDATA_OUT7
4
PLL_CTRL0
3
RSVD
2
MCLK
47
VREF
18
ADR_SEL
46
VDRIVE
19
COUT
20
CCLK
21
CLATCH
6
PLL_CTRL2
5
PLL_CTRL1
34
LRCLK_OUT1
33
ODVDD
29
SDATA_OUT0
28
ODVDD
26
LRCLK_OUT0
25
VDD
38
SDATA_OUT4
39
SDATA_OUT5
22
CDATA
30
SDATA_OUT1
44
VSUPPLY
7
PLL_GND
13
VDD
48
GND
23
RESETB
27
BCLK_OUT0
31
SDATA_OUT2
35
BCLK_OUT1
32
SDATA_OUT3
40
ODVDD
1
VDD
24
GND
36
GND
37
VDD
U1
AD1940YSTZ
C1
C2
C3
C4
C5
C6 C7
R1
1k0
C8
C9
L1
C10
+
C11
10uF
TP1
+
C12
10uF
C13
L2
C14
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
R2
56R0
1
2
3
Q1
ZXTP25040DFHTA
TP2
TP3
1
3
5
7
9
2
4
6
8
10
1211
J1
HEADER_12WAY_UNSHROUD
+
C15
10uF
+
C16
10uF
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
R3
56R0
2
B0
1
A0
3
O0
U2-A
74HC125
TP4
TP5
+
C17
10uF
TP6
R4
0R00
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
1
2
3
45
6
7
8
SW1
SPST_4SEC_SMD
1
2
3
4
5
6
7
8
9
10
R5
NET_BUS_8RES_SMD_10K0
1
3
5
7
9
2
4
6
8
10
J2
HEADER_10WAY_POL
D1
YELLOW
R6
604r
TP26
TP27
TP28
TP29
1940_SDATA_IN0
1940_SDATA_IN1
1940_SDATA_IN2
1940_SDATA_IN3
1940_BCLK_IN
1940_LRCLK_IN
RESET
SPI_COUT
SPI_CLATCH
SPI_CDATA
1940_PLL_CTRL1
1940_PLL_CTRL2
1939_MCLKO
SPDIF_RX_MCLK
MCLK
EXT_MCLK_H2
EXT_MCLK_H3
SPI_CCLK
1940_PLL_CTRL0
1940_ADR_SEL
EXT_MCLK_H1
D3V3
D3V3
1940_MCLK
1940_SDATA_IN0
1940_SDATA_IN1
1940_SDATA_IN2
1940_SDATA_IN3
1940_LRCLK_IN
1940_BCLK_IN
1940_SDATA_OUT0
1940_SDATA_OUT1
1940_SDATA_OUT2
1940_SDATA_OUT3
1940_SDATA_OUT4
1940_SDATA_OUT5
1940_SDATA_OUT6
1940_SDATA_OUT7
1940_LRCLK_OUT0
1940_BCLK_OUT0
1940_LRCLK_OUT1
1940_BCLK_OUT1
1940_PLL_CTRL0
1940_PLL_CTRL1
1940_PLL_CTRL2
1940_ADR_SEL
D3V3
SPI_COUT
SPI_CCLK
SPI_CLATCH
SPI_CDATA
SPI_CCLK
SPI_CDATA
SPI_COUT
SPI_CLATCH
VDD2P5V
INVDD3V3
1940_SDATA_OUT0
1940_SDATA_OUT1
1940_SDATA_OUT2
1940_SDATA_OUT3
1940_SDATA_OUT4
1940_SDATA_OUT7
1940_SDATA_OUT5
1940_SDATA_OUT6
1940_LRCLK_OUT0
1940_BCLK_OUT0
1940_LRCLK_OUT1
1940_BCLK_OUT1
Figure 19. AD1940 SigmaDSP and Communications Interface Schematics