Datasheet

EVAL-AD1940AZ Preliminary Technical Data
Rev. PrA | Page 10 of 30
J4 J5 J
6
J7
SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3
DON’TCARE DON’TCARE DON’TCARE SPDIF_RX_ DAT
A
Figure 16. Input Routing Jumpers -S/PDIF Configuration
Because the S/PDIF receiver is always a clock master to the
AD1940, the LRCLK_IN and BCLK_IN lines must be
connected to the S/PDIF receiver as shown in Figure 17.
J9J8
BCLK_INLRCLK_IN
SPDIF_BCLKSPDIF_L RCLK
Figure 17. LRCLK_IN/BCLK_IN Routing Jumpers - S/PDIF Configuration
The master clock must also be provided from the S/PDIF
receiver. For proper operation, J1 should have a jumper on
“DIR” and J3 should be set to “EXT.”
The S/PDIF receiver can only input data from one connector at
a time. To select the optical connector, set switch SW6 in the up
position. To select the coaxial electrical connector, set switch
SW6 in the down position.
With the jumpers configured as shown in Figure 16 and Figure
17, the S/PDIF inputs will appear in SigmaStudio as shown in
Figure 18.
S/PDIFINPUT
0
S/PDIFINPUT
1
Figure 18. S/PDIF Inputs in SigmaStudio
OUTPUT ROUTING
The AD1940 serial output ports are always connected to the
DACs, digital audio output headers, and S/PDIF transmitter.
These data signals do not require any jumpers or switches to be
output properly. The AD1940 serial output ports can be
configured as either masters or slaves. If the AD1940’s serial
output ports are configured as masters, then jumpers J10, J11,
J12 and J13 can be left disconnected. If the AD1940’s serial
output ports are configured as slaves, then jumpers J10, J11, J12
and J13 must be connected in order to output data. The
functionality of these jumpers is described in Table 5.
Table 5. Output Clock Routing
Component Function
J10
Connect LRCLK_OUT0 to LRCLK_IN. Must be
connected if serial output channels 0-7 are
configured as slaves and not externally
clocked.
J11
Connect BCLK_OUT0 to BCLK_IN. Must be
connected if serial output channels 0-7 are
configured as slaves and not externally
clocked.
J12
Connect LRCLK_OUT1 to LRCLK_IN. Must be
connected if serial output channels 8-15 are
configured as slaves and not externally
clocked.
J13
Connect BCLK_OUT1 to LRCLK_IN. Must be
connected if serial output channels 8-15 are
configured as slaves and not externally
clocked.
ANALOG AUDIO OUTPUTS
The EVAL-AD1940AZ has four stereo 1/8’ input jacks, allowing
for a total of 8 channels of analog audio output. Output
channels 0-7 are routed to the AD1939 DACs. The analog
outputs are hardwired to the AD1940’s serial output ports and
are always active.
The analog outputs 0-7 correspond to outputs 0-7 in
SigmaStudio.
EXTERNAL DIGITAL AUDIO (I
2
S/TDM) OUTPUTS
The EVAL-AD1940AZ has two external digital interface output
headers, J23 and J24, with connections to all eight
SDATA_OUT data lines, and two pairs of output LRCLK/BCLK
lines. These output headers are hardwired to the AD1940’s
serial output ports and are always active.
The I
2
S/TDM outputs 0-15 correspond to outputs 0-15 in
SigmaStudio.
S/PDIF TRANSMITTER
The EVAL-AD1940AZ has an S/PDIF transmitter with both
optical and coaxial electrical outputs. These outputs are
hardwired to the AD1940 and are always active.
The S/PDIF outputs 0-1 correspond to outputs 8-9 in
SigmaStudio.