Evaluation Board User Guide UG-045 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD1938 Four ADC/Eight DAC with PLL 192 kHz, 24-Bit Codec board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC USB port and provides SPI access to the evaluation board through a ribbon cable. A graphical user interface (GUI) program is provided for easy programming of the chip in a Microsoft® Windows® PC environment.
UG-045 Evaluation Board User Guide TABLE OF CONTENTS EVAL-AD1938AZ Package Contents ............................................ 1 Powering the Board.......................................................................3 Other Supporting Documentation ................................................. 1 Setting Up the Master Clock (MCLK)........................................4 Evaluation Board Overview ............................................................ 1 Configuring the PLL Filter ........
Evaluation Board User Guide UG-045 SETTING UP THE EVALUATION BOARD STANDALONE MODE It is possible to run the board and the AD1938 codec in standalone mode, which fixes the functionality of the AD1938 into the I2S data format, running at 256 × fS (default register condition). The ADC BCLK and LRCLK ports are flipped between slave and master (input and output) by tying SDA/COUT (Pin 24) to low or high.
UG-045 Evaluation Board User Guide C158 R178 R156 R156 C154 R155 08421-009 R172 EXT CLK IN JP30 HDR2 JP31 HDR1 R156 OSC R166 JP24 R175 193X_MCLKO J23 U22 R174 C168 C170 R175 EXT CLK IN 08421-010 C170 R169 JP28 Figure 10.
Evaluation Board User Guide UG-045 The ADC buffer circuit is designed with a switch (S1) that allows the user to change the voltage reference for all of the amplifiers. GND, CM, and FILTR can be selected as a reference; it is advisable to shut down the power to the board before changing this switch. The CM and FILTR lines are very sensitive and do not react well to a change in load while the AD1938 is active.
UG-045 Evaluation Board User Guide In this mode, the AD1938 ADC port generates BCLK and LRCLK when given a valid MCLK. For full flexibility of the AD1938, the part can be put in SPI control mode and programmed with the Automated Register Window Builder application (see Figure 4 for the appropriate jumper settings). Changing the registers and setting the DIP switches allow many possible configurations.
Figure 15. Settings Chart 1 Rev.
SPDIF_RX_8416 HDR1_DSDATA2 SPDIF_RX_8416 HDR1_DSDATA2 HDR1_DSDATA2 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA2 DAC_TDM_OUT DAC_TDM_OUT Aux ADC1 input TRISTATE SPDIF_RX_8416 SPDIF_RX_8416 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 TRISTATE Stereo Stereo Stereo Stereo Stereo N/A N/A Stereo/TDM Stereo Stereo TDM Dual- Line TDM DAC aux mode Stereo/TDM TRISTATE DAC_TDM_OUT Aux DAC2 output HDR1_DSDATA3 Aux ADC2 input TRISTATE
Evaluation Board User Guide UG-045 SCHEMATICS AND ARTWORK 08421-017 Figure 17. Board Schematics, Page 1—ADC Buffer Circuits Rev.
UG-045 Evaluation Board User Guide 08421-018 Figure 18. Board Schematics, Page 2—Serial Digital Audio Interface Headers with MCLK Direction Switching Rev.
Evaluation Board User Guide UG-045 08421-019 Figure 19. Board Schematics, Page 3—S/PDIF Receive and Transmit Interfaces Rev.
UG-045 Evaluation Board User Guide 08421-020 Figure 20. Board Schematics, Page 4—Serial Digital Audio Routing and Control CPLD Rev.
Evaluation Board User Guide UG-045 08421-021 Figure 21. Board Schematic, Page 5—AD1938 with MCLK Selection Jumpers Rev.
Evaluation Board User Guide 08421-022 UG-045 Figure 22. Board Schematics, Page 6—Daughter Card Interface, Useful as Test Points Rev.
Evaluation Board User Guide UG-045 08421-023 Figure 23. Board Schematics, Page 7—DAC Buffer Circuits Rev.
UG-045 Evaluation Board User Guide 08421-024 Figure 24. Board Schematics, Page 8—SPI Control Interface Rev.
UG-045 08421-025 Evaluation Board User Guide Figure 25. Board Schematics, Page 9—Power Supply Rev.
Evaluation Board User Guide 08421-026 UG-045 Figure 26. Top Assembly Layer Rev.
UG-045 08421-027 Evaluation Board User Guide Figure 27. Bottom Assembly Layer Rev.
UG-045 Evaluation Board User Guide CPLD CODE MODULE TITLE IF_Logic 'AD1938 EVB Input Interface Logic' //=================================================================================== // FILE: // REVISION DATE: AD1938_pld_revE.
Evaluation Board User Guide UG-045 BCLK_8416 pin 60 istype 'com'; LRCLK_8416 pin 59 istype 'com'; SOMS_RX,SFSEL1_RX,SFSEL0_RX,RMCKF_RX pin 66,67,64,65 istype 'com'; // S/PDIF Tx CS8404 pins SDATA_8406 'com'; pin 50 istype BCLK_8406,LRCLK_8406 pin 53, 54 istype 'com'; MCLK_8406 'com'; pin 49 istype APMS_TX,SFMT1_TX,SFMT0_TX pin 55,56,58 istype 'com'; CPLD_MCLK 'com'; pin 89 istype // AD1938 SPI port pins //CCLK,CDATA,CLATCH pin 84, 83, 85 istype 'com'; //COUT pin 82 istype 'com'; //CLATC
UG-045 Evaluation Board User Guide //================================================================================ "MACROS // Switch S3, DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL = ( MODE22 & MODE23); ADC_HDR_DATA2_DATA1 = ( MODE22 & !MODE23); ADC_HDR_TDM = (!MODE22 & MODE23); ADC_HDR_AUX = (!MODE22 & !MODE23); S/PDIF_OUT_MUX = MODE24; // HEX Switch S4 // S4 position 0, DAC_RX_ALL = ( MODE14 & MODE13 & MODE12 & MODE11); // S4 position 1, DAC_RX_1 = ( MODE14 & MODE13 & MODE12 & !MODE11); //
Evaluation Board User Guide UG-045 // S4 position B, DAC_DUAL_TDM = ( !MODE14 & MODE13 & DAC_HDR1_AUX = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // S4 position C, MODE12 & MODE11); // S4 position D, NA3 = ( !MODE14 & !MODE13 & MODE12 & !MODE11); // S4 position E, NA4 = ( !MODE14 & !MODE13 & !MODE12 & MODE11); // S4 position F, DAC_DATA_HIZ = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // Switch S2 DAC_S/PDIF = (DAC_CLK_SRC1 & DAC_CLK_SRC0); DAC_HDR1 = (DAC_CLK_SRC1 & !DAC_CLK_SRC0
UG-045 // Evaluation Board User Guide M3_8414 = 0; // CS8404 Tx interface mode select APMS_TX = 0; // Tx serial port is always slave in this application SFMT1_TX = 0; // Tx data format is I2S always SFMT0_TX = 1; // M0_8404 = 0; // M1_8404 = 0; // M2_8404 = 1; // I2S format only // divide 256Fs clock by 2 for 128Fs clock to the the S/PDIF Tx // Qdivide.clk = CPLD_MCLK; // Qdivide.
Evaluation Board User Guide UG-045 HDR1_DSDATA4.oe = (DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX); HDR1_ASDATA2.
UG-045 Evaluation Board User Guide ORDERING INFORMATION BILL OF MATERIALS Table 1.
Evaluation Board User Guide Qty 16 3 Designator R56, R57, R65, R66, R88, R89, R140, R154, R179, R183, R213, R216, R228 to R231 C25, C31, C45, C53, C169, C181, C190, C198 R3, R11, R58 1 C125 4 R5, R52, R53, R75 1 C120 33 R38 1 R129 8 3 C24, C34, C44, C56, C167, C185, C189, C201 C11, C14, C22, C26, C27, C30, C32, C35, C41, C46, C47, C52, C54, C57, C63, C66, C72, C75, C80, C105, C119, C133, C139, C148, C152, C164, C172, C179, C191, C196 C12, C18, C19 4 R83, R96, R148, R163 20 1 R103, R104,
UG-045 Evaluation Board User Guide Qty 1 Designator Y1 Description Crystal, 12.
Evaluation Board User Guide Qty 2 2 1 1 Designator SW2, SW3 S2, S3 S6 U5 1 60 U7 TP1 to TP6, TP8 to TP10, TP12 to TP15, TP17, TP19 to TP23, TP25 to TP52, TP54 to TP60, TP62, TP64 to TP68 UG-045 Description SPDT slide switch, PC mount 8-position SPST SMD switch, flush, actuated Tact switch, 6 mm, gull wing 15 Mb/sec fiber optic receiving module with shutter Fiber optic transmit module, 15 Mb/sec Mini test point white, 0.1 inch, OD Rev.
UG-045 Evaluation Board User Guide NOTES Rev.
Evaluation Board User Guide UG-045 NOTES Rev.
UG-045 Evaluation Board User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
