Datasheet

UG-040 Evaluation Board User Guide
Rev. 0 | Page 8 of 32
ROTARY AND DIP SWITCH SETTINGS
08411-017
AD193X/ADAU132X Rev-E Evaluation Board Configuration: (* indicates default setting)
1) DIP Switch S2 Position-8 (SPDIF_RX_TX reset) must be toggled after power-up for proper operation of the SPDIF receiver and transmitter.
2) The AD193x evalution board defaults the AD193x codec to standalone mode preventing SPI/I
2
C operation. The J5, J6, J7, and J8 header jumpers can be changed for SPI/I
2
C operation.
ADC and DAC Serial Clock (BCLK, LRCLK) Source Selection and Routing (Switch S2)
1) DIP Switch S2 cont
rols the AD193x ADC and DAC serial clock source selection. One of four clock sources is selected based on the setting. SPDIF Receiver
CS8416, Header Connector HDR1, ADC serial clocks, or DAC serial clock can be the clock source. ADC and DAC serial clock selection is controlled independently.
2) The AD193x master clock source should be selected using the JP28, JP29, JP30, and JP31 header jumpers such that the MCLK source is in sync with the DAC/ADC serial clock and data source.
DIP Switch S2 position:
Position-1 Des
cription
Off* Enable Enable ADC clocks
On Disable
Tristate ADC clocks
Position-2 Position-3
ABCLK Source ALRCLK Source SPDIF_Rx Clocks SPDIF_Tx Clocks HDR1 Clocks ADC Cl ocks DAC Clocks
Off* Off* SPDIF_RX_8416 SPDIF_RX_8416 Master Slave Slave Slave N/A Off On HDR1_ABCLK HDR1_ALRCLK Slave Slave Master Slave N/A
On Off ADC-ABCLK ADC-ALRCLK Slave Slave Slave Master N/A
On On DAC-DBCLK DAC-DLRCLK Slave Slave Slave Slave Master Position-4 Description
Off* Enable Enable DAC clocks
On Disable
Tristate DAC clocks
Position-5 Position-6
DBCLK Source DLRCLK Source SPDI
F_Rx Clocks SPDIF_Tx Clocks HDR1 Clocks ADC Cl ocks DAC Clocks
Off* Off* SPDIF_RX_8416 SPDIF_RX_8416 Master Slave Slave N/A Slave
Off On HDR1_DBCLK HDR1_DLRCLK Slave Slave Master N/A Slave
On Off ADC-ABCLK ADC-ALRCLK Slave Slave Slave Master Slave
On On DAC-DBCLK DAC-DLRCLK Slave Slave Slave N/A Master
Position-7 Description SPDIF_TX CS8406 MCLK Jumper Settings
SPDIF_RX_TX MCLK Rate
JP10 JP9
Off* SPDIF_RX_TX MCLK Rate = 256xf
S
0 0
On SPDIF_RX_TX MCLK Rate = 128xf
S
0 1
Position-8
Description
SPDIF_TX_RX RESETB
Off* SPDIF_RX_TX in active mode (Note: This position must be toggled
after power-up for proper operation.)
On SPDIF_RX_TX in reset mode SPDIF RX - CS8416 Jumpers
JP1 JP2 JP3 0 = Normal update rate phase detector, increased clock jitter 0 = NVERR selected 0 = Emphasis audio match off
1 = High update rate phase detector, low clock jitter 1 = RERR selected 1 = Emphasis audio match on
SPDIF TX - CS8406 Jumpers SPDIF_TX CS8406 MCLK Rate Jumper Settings
JP18 JP10 JP9
y bit in the outgoing AES3 transmitted datatidilavehtfoetatsehtsenimretedtupninipVeht=0 0 0 SPDIF_TX MCLK Rate = 256xf
S
y bit in the outgoing AES3 transmitted datatidilavehtfoetatsehtsenimretedtupninipVeht=1 0
1 SPDIF_TX MCLK Rate = 128xf
S
Figure 17. Settings Chart 1