Datasheet
Evaluation Board User Guide UG-040
Rev. 0 | Page 5 of 32
08411-010
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18 JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 10. External Clock In as Master; the AD1939 and CPLD as Slaves
08411-011
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18 JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 11. Active On-Board Oscillator as Master; the AD1939 and
CPLD as Slaves
The MCLK configurations shown in Figure 12 and Figure 13
use the AD1937/AD1939 MCLKO port to drive the CPLD and,
possibly, the HDRs. The passive crystal runs the AD1937/AD1939
at 12.288 MHz. Figure 13 shows the MCLKI shut off; this is the
case when the PLL is set to lock to LRCLK instead of to MCLK.
08411-012
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 12. Passive Crystal; the AD1939 Is Master and the CPLD Is Slave from
the MCLKO Port
08411-013
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 13. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and
CPLD Is Slave to the MCLKO Port
CONFIGURING THE PLL FILTER
The PLL for the AD1937/AD1939 can run from either MCLK
or LRCLK, according to its setting in the PLL and Clock Control 0
register, Bits[6:5]. The matching RC loop filter must be con-
nected to LF (Pin 61) using JP15. See Figure 14 and Figure 15
for the jumper positions.