Datasheet
UG-040 Evaluation Board User Guide
Rev. 0 | Page 4 of 32
You can now open the Automated Register Window Builder
application and load the file for the part onto your evaluation
board.
POWERING THE BOARD
The AD1937/AD1939 evaluation board requires power supply
input of ±12 V dc and ground to the three binding posts; +12 V
draws ~250 mA, and −12 V draws ~100 mA. The on-board
regulators provide two 3.3 V rails and one 5.0 V rail. The 3.3 V
rails supply AVDD and DVDD for the AD1937/AD1939; DVDD
also supplies power for the peripheral active components on the
board. The 5.0 V rail provides voltage only to the AD1937/
AD1939 internal regulator, which consists of a PNP pass tran-
sistor and a few passive components. The PNP is driven into
3.3 V regulation by the VDRIVE pin of the AD1937/AD1939,
with the VSUPPLY and VSENSE pins acting as power and
feedback for the regulator. An appropriate sized PNP can supply
3.3 V to the AVDD and DVDD pins of the AD1937/AD1939.
The jumper blocks are shown in Figure 6 and Figure 7.
08411-006
MAIN REGS
C122
R117
C96
Q1
AVDD2
AVDD1
R102
C97
DVDD
193X REG
193X REG
JP6 JP7
JP15
JP5
ENABLE
DISABLE
Figure 6. AD1939 Main Regulators Active
08411-007
MAIN REGS
C122
R117
C96
Q1
AVDD2
AVDD1
R102
C97
DVDD
193X REG
193X REG
JP6 JP7
JP15
JP5
ENABLE
DISABLE
Figure 7. AD1939 Internal Regulator Active
The first step in using the AD1937/AD1939 internal regulator is
to provide power to the regulator circuit by moving the AD1937/
AD1939 REG jumper from DISABLE to ENABLE, as shown in
Figure 7. Three discrete jumpers allow the AD1937/AD1939 to
be run from either the main AVDD and DVDD regulators or
the AD1937/AD1939 internal regulator. These jumpers also
allow measurement of current drawn by the individual sections
of the AD1937/AD1939. The only components on the AD1937/
AD1939 side of the jumper are the AD1937/AD1939 and the
supply decoupling capacitors.
SETTING UP THE MASTER CLOCK (MCLK)
The AD1937/AD1939 evaluation board has a series of jumpers
that give the user great flexibility in the MCLK clock source of
the AD1937/AD1939. MCLK can come from six different
sources: passive crystal, active oscillator, external clock in, S/PDIF
receiver, and two header connections. Note that the complex
programmable logic device (CPLD) on the board must have a
valid clock source; the frequency is not critical. These jumper
blocks can assign a clock to the CPLD as well. Most applications
of the board use MCLK from either the S/PDIF receiver or one
of the header (HDR) inputs. Figure 8 to Figure 10 show the on-
board active oscillator disabled so that it does not interfere with
the selected clock. The clock feed to the CPLD comes directly
from the clock source.
Note that, if the HDR connectors are to be driven with MCLK
from a source on the evaluation board, SW2 and/or SW3 must
be switched from the IN position to the OUT position.
08411-008
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18 JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 8. S/PDIF Receiver as MCLK Master; the AD1939 and CPLD as Slaves
08411-009
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP24
OSC
R155
R156
C154
C153
MCLKI
XTAL
MCLKO
XTAL
R166
R178
MCLKI BUS
MCLKO BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18 JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 9. HDR1 as MCLK Master; the AD1939, CPLD, and HDR2 as Slaves