Evaluation Board User Guide UG-040 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD1937/AD1939 Four ADC/Eight DAC with PLL 192 kHz, 24-Bit Codec EVAL-AD1937AZ/EVAL-AD1939AZ PACKAGE CONTENTS through an SPI or I2C interface. A small external interface board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC USB port and provides I2C and SPI access to the evaluation board through a ribbon cable.
UG-040 Evaluation Board User Guide TABLE OF CONTENTS EVAL-AD1937AZ/EVAL-AD1939AZ Package Contents ........... 1 Powering the Board.......................................................................4 Other Supporting Documentation ................................................. 1 Setting Up the Master Clock (MCLK)........................................4 Evaluation Board Overview ............................................................ 1 Configuring the PLL Filter ...........................
Evaluation Board User Guide UG-040 SETTING UP THE EVALUATION BOARD The Automated Register Window Builder controls the AD1937/AD1939 and is available at www.analog.com/AD1937 or www.analog.com/AD1939. 2. Figure 3. Standalone Master Mode At www.analog.com/AD1937 or www.analog.com/AD1939, find the Resources & Tools list. In the list, find Evaluation Boards & Development Kits and click Evaluation Boards/Tools to open the provided ARWBvXX.zip file. Double-click the provided .
UG-040 Evaluation Board User Guide 193X_MCLKI DISABLE JP19 JP20 MCLKO C147 XTAL R160 JP22 OSC Q1 L7 C153 1938_MCLKI R166 JP5 JP6 JP7 R102 C97 J23 U22 JP28 EXT CLK Figure 6.
Evaluation Board User Guide UG-040 J23 R175 EXT CLK IN 08411-010 JP31 HDR1 Figure 10.
Evaluation Board User Guide CM FILTER VREF SELECT IN1R+ IN1R– 08411-016 TP34 R101 R107 GND JP4 C89 C88 U14 C99 C74 TP32 C83 C82 R106 R76 C68 C77 R81 JP12 JP11 R86 C76 S1 IN1L– R90 C80 IN1L+ TP28 JP13 IN1R C75 TP30 R93 R97 C79 MCLK LRCLK JP15 C131 R85 R87 08411-015 C114 C125 R138 C67 U12 C69 R84 PLL SELECT C120 TP26 C65 C64 TP25 Figure 14.
Evaluation Board User Guide UG-040 For the full flexibility of the AD1937/AD1939, the part can be put in SPI/I2C control mode and programmed with the Automated Register Window Builder application (see Figure 4 and Figure 5 for the appropriate jumper settings). Changing the registers and setting the DIP switches allow many possible configurations.
Enable ADC clocks Tristate ADC clocks Enable Disable Position-3 Off* On Off On Off* On Position-2 Off* Off On On Enable DAC clocks Tristate DAC clocks Enable Disable Position-6 Off* On Off On Off* On Position-5 Off* Off On On Figure 17. Settings Chart 1 Rev.
SPDIF_RX_8416 HDR1_DSDATA2 SPDIF_RX_8416 HDR1_DSDATA2 HDR1_DSDATA2 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA2 DAC_TDM_OUT DAC_TDM_OUT Aux ADC1 input TRISTATE SPDIF_RX_8416 SPDIF_RX_8416 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 TRISTATE Stereo Stereo Stereo Stereo Stereo N/A N/A Stereo/TDM Stereo Stereo TDM Dual- Line TDM DAC aux mode Stereo/TDM TRISTATE DAC_TDM_OUT Aux DAC2 output HDR1_DSDATA3 Aux ADC2 input TRISTATE
UG-040 Evaluation Board User Guide SCHEMATICS AND ARTWORK 08411-019 Figure 19. Board Schematics, Page 1—ADC Buffer Circuits Rev.
Evaluation Board User Guide UG-040 08411-020 Figure 20. Board Schematics, Page 2—Serial Digital Audio Interface Headers with MCLK Direction Switching Rev.
UG-040 Evaluation Board User Guide 08411-021 Figure 21. Board Schematics, Page 3—S/PDIF Receive and Transmit Interfaces Rev.
Evaluation Board User Guide UG-040 08411-022 Figure 22. Board Schematics, Page 4—Serial Digital Audio Routing and Control CPLD Rev.
UG-040 Evaluation Board User Guide 08411-023 Figure 23. Board Schematics, Page 5—AD1937/AD1939 with MCLK Selection Jumpers Rev.
UG-040 08411-024 Evaluation Board User Guide Figure 24. Board Schematics, Page 6—Daughter Card Interface, Useful as Test Points Rev.
UG-040 Evaluation Board User Guide 08411-025 Figure 25. Board Schematics, Page 7—DAC Buffer Circuits Rev.
UG-040 08411-026 Evaluation Board User Guide Figure 26. Board Schematics, Page 8—SPI and I2C Control Interface Rev.
Evaluation Board User Guide 08411-027 UG-040 Figure 27. Board Schematics, Page 9—Power Supply Rev.
UG-040 08411-028 Evaluation Board User Guide Figure 28. Top Assembly Layer Rev.
Evaluation Board User Guide 08411-029 UG-040 Figure 29. Bottom Assembly Layer Rev.
Evaluation Board User Guide UG-040 CPLD CODE MODULE TITLE IF_Logic 'AD1939 EVB Input Interface Logic' //=================================================================================== // FILE: // REVISION DATE: AD1939_pld_revE.
UG-040 Evaluation Board User Guide BCLK_8416 pin 60 istype 'com'; LRCLK_8416 pin 59 istype 'com'; SOMS_RX,SFSEL1_RX,SFSEL0_RX,RMCKF_RX pin 66,67,64,65 istype 'com'; // S/PDIF Tx CS8404 pins SDATA_8406 'com'; pin 50 istype BCLK_8406,LRCLK_8406 pin 53, 54 istype 'com'; MCLK_8406 'com'; pin 49 istype APMS_TX,SFMT1_TX,SFMT0_TX pin 55,56,58 istype 'com'; CPLD_MCLK 'com'; pin 89 istype // AD1939 SPI port pins //CCLK,CDATA,CLATCH pin 84, 83, 85 istype 'com'; //COUT pin 82 istype 'com'; //CLATCH2
Evaluation Board User Guide UG-040 //================================================================================ "MACROS // Switch S3, DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL = ( MODE22 & MODE23); ADC_HDR_DATA2_DATA1 = ( MODE22 & !MODE23); ADC_HDR_TDM = (!MODE22 & MODE23); ADC_HDR_AUX = (!MODE22 & !MODE23); S/PDIF_OUT_MUX = MODE24; // Hex Switch S4 // S4 position 0, DAC_RX_ALL = ( MODE14 & MODE13 & MODE12 & MODE11); // S4 position 1, DAC_RX_1 = ( MODE14 & MODE13 & MODE12 & !MODE11); //
UG-040 Evaluation Board User Guide // S4 position B, DAC_DUAL_TDM = ( !MODE14 & MODE13 & DAC_HDR1_AUX = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // S4 position C, MODE12 & MODE11); // S4 position D, NA3 = ( !MODE14 & !MODE13 & MODE12 & !MODE11); // S4 position E, NA4 = ( !MODE14 & !MODE13 & !MODE12 & MODE11); // S4 position F, DAC_DATA_HIZ = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // Switch S2 DAC_S/PDIF = (DAC_CLK_SRC1 & DAC_CLK_SRC0); DAC_HDR1 = (DAC_CLK_SRC1 & !DAC_CLK_SRC0
Evaluation Board User Guide // UG-040 M3_8414 = 0; // CS8404 Tx interface mode select APMS_TX = 0; // Tx serial port is always slave in this application SFMT1_TX = 0; // Tx data format is I2S always SFMT0_TX = 1; // M0_8404 = 0; // M1_8404 = 0; // M2_8404 = 1; // I2S format only // divide 256Fs clock by 2 for 128Fs clock to the S/PDIF Tx // Qdivide.clk = CPLD_MCLK; // Qdivide.
UG-040 Evaluation Board User Guide HDR1_DSDATA4.oe = (DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX); HDR1_ASDATA2.
Evaluation Board User Guide UG-040 ORDERING INFORMATION BILL OF MATERIALS Table 1.
UG-040 Qty 16 3 Designator R56, R57, R65, R66, R88, R89, R140, R154, R179, R183, R213, R216, R228 to R231 C24, C25, C31, C34, C44, C45, C53, C56, C167, C169, C181, C185, C189, C190, C198, C201 R3, R11, R58 1 C125 4 R5, R52, R53, R75 1 C120 33 R21, R22, R26, R27, R33 to R35, R37 to R39, R41, R46, R50, R62, R68, R69, R71, R173, R176, R182, R184, R193, R195, R197, R199, R202, R204, R209, R211, R219 to R221, R223 R23, R25, R32, R36, R42, R45, R61, R70, R177, R181, R192, R198, R205, R208, R218, R222 R1
Evaluation Board User Guide Qty Designator 1 R67 16 1 C22, C27, C32, C35, C41, C47, C54, C57, C165, C173, C182, C186, C187, C192, C199, C202 Y1 1 1 1 1 U15 U23 U1 J2 1 J3 1 J4 2 1 1 2 1 1 6 1 2 4 1 UG-040 Manufacturer Part Number Rohm MCR03EZPFX90R9 Murata ENA GRM1885C1H911JA01D Crystal, 12.
UG-040 Evaluation Board User Guide Qty 1 Designator U10 Description 110 Ω AES/EBU transformer 2 1 2 2 U18, U22 U4 SW2, SW3 S2, S3 1 1 S6 U5 1 69 U7 TP1 to TP69 Buffer, three-state single gate Octal, three-state buffer/driver SPDT slide switch, PC mount 8-position, SPST SMD switch, flush, actuated Tact switch, 6 mm, gull wing 15 Mb/sec fiber optic receiving module with shutter 15 Mb/sec fiber optic transmit module, Mini test point, white, 0.
Evaluation Board User Guide UG-040 NOTES Rev.
UG-040 Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD.
