Datasheet

AD1871
–8–
REV. 0
CONTROL INTERFACE (SPI) TIMING
Mnemonic Description Min Typ Max Unit Comment
t
CCH
CCLK High Width 40 ns
t
CCL
CCLK Low Width 40 ns
t
CCP
CCLK Period 80 ns
t
CDS
CDATA Setup Time 10 ns To CCLK Rising
t
CDH
CDATA Hold Time 10 ns From CCLK Rising
t
CLS
CLATCH Setup Time 10 ns To CCLK Rising
t
CLH
CLATCH Hold Time 10 ns From CCLK Rising
t
COE
COUT Enable 15 ns From CLATCH Falling
t
COD
COUT Delay 20 ns From CCLK Falling
t
COTS
COUT Three-State 25 ns From CLATCH Rising
t
CCH
t
CCL
CCLK
CLATCH
CIN
COUT
D15 D14 D12 D11 D10 D07 D06 D04 D03 D02 D01 D00D13 D09
D08
D08 D07 D06 D05 D04 D03 D02 D01 D00D09
D05
t
CHD
t
CSU
t
CCL
t
CLH
Figure 7. Control Interface Timing
DIGITAL I/O
Parameter Min Typ Max Unit
Input Voltage High (V
IH
) 2.4 V
Input Voltage Low (V
IL
) 0.8 V
Input Leakage (I
IH
@ V
IH
= 5 V) 10 mA
Input Leakage (I
IL
@ V
IL
= 0 V) 10 mA
Output Voltage High (V
OH
@ I
OH
= –2 mA) ODVDD – 0.4 V V
Output Voltage Low (V
OL
@ I
OL
= +2 mA) 0.4 V
Input Capacitance 15 pF
POWER
Parameter Min Typ Max Unit
Supplies
Voltage, AVDD, and DVDD 4.5 5 5.5 V
Voltage, ODVDD 2.7 5.5 V
Analog Current 40 45 mA
Analog Current—Power-Down (MCLK Running) 4.0 6.0 mA
Digital Current, DVDD 18 22 mA
Digital Current, ODVDD 0.5 1.0 mA
Digital Current—Power-Down (MCLK Running) DVDD* 0.8 2.0 mA
Digital Current—Power-Down (MCLK Running) ODVDD* 1.0 15.0 mA
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins –86 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB
*RESET held low.
TEMPERATURE RANGE
Parameter Min Typ Max Unit
Specifications Guaranteed 25 ∞C
Functionality Guaranteed –40 +105 ∞C
Storage –65 +150 ∞C
Specifications subject to change without notice.