Datasheet

REV. 0
–7–
AD1871
DATA INTERFACE TIMING (CASCADE MODE–MASTER)
Mnemonic Description Min Typ Max Unit Comment
t
BCHDC
BCLK High Delay 20 ns From MCLK Rising
t
BCLDC
BCLK Low Delay 20 ns From MCLK Falling
t
BLRDC
LRCLK Delay 10 ns From BCLK Rising
t
BDDC
DOUT Delay 10 ns From BCLK Rising
t
BDIS
DIN Setup 10 ns To BCLK Rising
t
BDIH
DIN Hold 10 ns From BCLK Rising
LRCLK
MCLK
DOUT
BCLK
t
BCHDC
t
BCLDC
t
BLRDC
t
BDDC
Figure 4. Master Cascade Interface Timing
DATA INTERFACE TIMING (CASCADE MODE–SLAVE)
Mnemonic Description Min Typ Max Unit Comment
t
BCHC
BCLK High Width 30 ns
t
BCLC
BCLK Low Width 30 ns
t
BDSDC
DOUT Delay 20 ns From BCLK Rising
t
LRSC
LRCLK Setup 10 ns To BCLK Rising
t
LRHC
LRCLK Hold 5 ns From BCLK Rising
t
BDIS
DIN Setup 10 ns To BCLK Rising
t
BDIH
DIN Hold 10 ns From BCLK Rising
LRCLK
DOUT
BCLK
t
LRSC
t
BDSDC
t
BCHC
t
BCLC
t
LRHC
Figure 5. Slave Cascade Interface Timing
DATA INTERFACE TIMING (MODULATOR MODE)
Mnemonic Description Min Typ Max Unit Comment
t
MOCH
MODCLK High Width MCLK ns
t
MOCL
MODCLK Low Width MCLK ns
t
MHDD
MOD DATA High Delay 30 ns From MCLK Rising
t
MLDD
MOD DATA Low Delay 20 ns From MCLK Falling
t
MMDR
MODCLK Delay Rising 30 ns MCLK Falling to MODCLK Rising
t
MMDF
MODCLK Delay Falling 20 ns MCLK Falling to MODCLK Falling
D[0–3]
MODCLK
t
MHDD
t
MOCH
t
MOCL
t
MLDD
Figure 6. Modulator Mode Timing