Datasheet

AD1871
–6–
REV. 0
DATA INTERFACE TIMING (STANDALONE MODE–SLAVE)
Mnemonic Description Min Typ Max Unit Comment
t
BCH
BCLK High Width 30 ns
t
BCL
BCLK Low Width 30 ns
t
BDSD
DOUT Delay 20 ns From BCLK Falling
t
LRS
LRCLK Setup 10 ns To BCLK Rising
t
LRH
LRCLK Hold 5 ns From BCLK Rising
t
BDSD
BCLK
LRCLK
DOUT
LEFT-JUSTIFIED
MO
DE
DOUT
RIGHT-JUSTIFIED
MO
DE
LSB
DOUT
I
2
S-JUSTIFIED
MO
DE
t
BCH
t
DBP
t
BCL
MSB
MSB–1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LRS
Figure 3. Slave Data Interface Timing