Datasheet
REV. 0
–5–
AD1871
DATA INTERFACE TIMING (STANDALONE MODE–MASTER)
Mnemonic Description Min Typ Max Unit Comment
t
BDLY
BCLK Delay 20 ns From MCLK Rising
t
BLDLY
LRCLK Delay to Low 10 ns From BCLK Falling
t
BDDLY
DOUT Delay 10 ns From BCLK Falling
t
BDDLY
BCLK
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
DOUT
RIGHT-JUSTIFIED
MODE
LSB
DOUT
I
2
S-JUSTIFIED
MODE
t
BDLY
t
BLDLY
MSB
MSB–
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
MCLK
1
Figure 2. Master Data Interface Timing