Datasheet

REV. 0
AD1871
–21–
Table III. Control/Status Word Format
15-12 11 10 9 6 5 4 3210
Address R/W Reserved Control/Status Data Bits (9–0)
CCLK
CLATCH
CIN
COUT
D15 D14 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00D13
Figure 20. Writing to Register Using Control Port
D08 D07 D06 D05 D04 D03 D02 D01 D00D09
CCLK
CLATCH
CIN
COUT
D15 D14 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00D13
Figure 21. Reading from Register Using Control Port
Table IV. Control Register I (Address 0000b, Write Only)
15–12 11 10 9 8 7 6 5 4 3 2 1 0
0000 0 0 PRE HPE PD AMC AGL2 AGL1 AGL0 AGR2 AGR1 AGR0
9 PRE Peak Reading Enable (0 = Disabled (Default); 1 = Enabled)
8 HPE High-Pass Filter Enable (0 = Disabled (Default); 1 = Enabled)
7PD Power-Down Control (1 = Power-Down; 0 = Normal Operation (Default))
6 AMC ADC Modulator Clock (1 = 64 ¥ f
S
; 0 = 128 ¥ f
S
(Default))
5–3 AGL2–AGL0 Input Gain (Left Channel, see Table V)
2–0 AGR2–AGL0 Input Gain (Right Channel, see Table V)
Control Register I
Control Register I contains bit settings for control of analog
front end gain, modulator clock selection, power-down control,
high-pass filtering, and peak hold.
Analog Gain Control
The AD1871 features an optional analog front end with select-
able gain. Gain is selected using three control bits for each channel,
giving five separate and independent gain settings on each channel.
Bits 2 through 0 (AGR2–AGR0) set the analog gain for the right
channel, while Bits 5 through 3 (AGL2–AGL0) set the analog
gain for the left channel. Table V shows the analog gain corre-
sponding to the bit settings in AGx2–ADx0.
Table V. Analog Gain Settings
AGx2 AGx1 AGx0 Gain (dB)
000 0 (Default)
001 3
010 6
011 9
100 12
101 0
110 0
111 0