Datasheet

AD1871
–10–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin Input/
No. Output Mnemonic Description
1I MCLK Master Clock. The master clock input determines the sample rate of the device. MCLK
can be 256, 512, or 768 times the sampling frequency.
2I CCLK
1
Control Port Bit Clock—clock signal for control port (SPI) interface. This pin is recon-
figured in the External Control Mode (Pin XCTRL is high), see below.
3 I/O COUT
1, 2
Control Port Data Out—serial data output from the control port (SPI) interface (in read-
back). This pin is reconfigured in the External Control Mode (Pin XCTRL is high), see
below; or in Modulator Mode (Bit MME of Control Register II is set), see below.
4I CIN
1
Control Port Data Input—serial data input for control port (SPI) interface. This pin is
reconfigured in the External Control Mode (Pin XCTRL is high), see below.
5I CLATCH
1
Control Port Frame Sync—frame sync (framing signal) for control port (SPI) interface.
This pin is reconfigured in the External Control Mode (Pin XCTRL is high), see below.
6I DVDD 5 V Digital Core Supply
7I DGND Digital Ground
8I XCTRL External Control Enable. This pin is used to select the Control Mode for the device.
When XCTRL is low, control is via the SPI compatible control port (Pins CCLK, CLATCH,
CIN, and COUT). When XCTRL is enabled (high), control of several device functions
is possible by hardware pin strapping (Pins 256/512, M/S, DF1, and DF0). In
External
Control Mode, all other functions are in default state (please refer to the Control Register
Descriptions and External Control section).
9I AVDD 5 V Analog Supply
10 I VINLN Left Channel, Negative Input (via MUX/PGA)
11 I VINLP Left Channel, Positive Input (via MUX/PGA)
12 I/O CAPLN Left External Filter Capacitor (Negative Input to Modulator)
13 I/O CAPLP Left External Filter Capacitor (Positive Input to Modulator)
14 O VREF
Reference Voltage Output. It is recommended to connect a capacitor combination of 10 mF
in parallel with 0.1 mF between VREF and AGND (Pin 15). (See Layout Recommendations.)
15 I AGND Analog Ground
16 I/O CAPRP Right External Filter Capacitor (Positive Input to Modulator)
17 I/O CAPRN Right External Filter Capacitor (Negative Input to Modulator)
18 I VINRP Right Channel, Positive Input (via MUX/PGA)
19 I VINRN Right Channel, Negative Input (via MUX/PGA)
20 I AGND Analog Ground
21 I CASC Cascade Enable. This pin enables cascading of up to four AD1871 devices to a single
DSP serial port (see Cascading section).
22 I DGND Digital Ground
23 I ODVDD
Digital Interface Supply. The digital interface can operate from 3.3 V to 5.0 V (nominal).
24 I RESET Reset
25 I/O DIN
2
Serial Data Input. Serial data input pin, only valid when the device is configured in Cas-
cade Mode (Pin CASC is high). This pin is reconfigured in Modulator Mode (Bit MME
of Control Register II is set), see below.
26 O DOUT
2
Audio Serial Data Output. This pin is reconfigured in Modulator Mode (Bit MME of
Control Register II is set), see below.
27 I/O BCLK
2
Audio Serial Bit Clock. The bit clock is the audio data serial clock and determines the
rate of audio data transfer. This pin is reconfigured in Modulator Mode (Bit MME of
Control Register II is set), see below.
28 I/O LRCLK
2
Left/Right Clock. This clock, also known as the word clock, determines the sampling rate.
It is an output or input depending on the status of Master/Slave. This pin is reconfigured
in Modulator Mode (Bit MME of Control Register II is set), see below.
NOTES
1
External Control Mode (See pg 11)
2
Modulator Mode (See pg 11)