Datasheet

DAC8512
–4–
REV. A
CLR
t
csh
D11 D10 D9 D8 D7 D6 D5 D3D4 D1D2 D0
t
ld2
t
css
t
ld1
t
S
t
dh
t
ds
t
cl
t
ch
t
ldw
t
s
t
clrw
±1 LSB
ERROR BAND
SDI
CLK
CS
SDI
CLK
FS
ZS
V
OUT
LD
LD
Figure 1. Timing Diagram
DATA
SHIFT
REGISTER
ESD PROTECTION DIODES TO V
DD
AND GND
SDI
CS
CLK
Figure 2. Equivalent Clock Input Logic
Table I. Control-Logic Truth Table
CS
2
CLK
2
CLR LD Serial Shift Register Function DAC Register Function
H X H H No Effect Latched
L L H H No Effect Latched
L H H H No Effect Latched
L ↑+ H H Shift-Register-Data Advanced One Bit Latched
↑+ L H H Shift-Register-Data Advanced One Bit Latched
HX H↓– No Effect Updated with Current Shift Register Contents
H X H L No Effect Transparent
H X L X No Effect Loaded with All Zeros
HX ↑+ H No Effect Latched All Zeros
NOTES
l
↑+ positive logic transition; ↓– negative logic transition; X = Don’t Care.
2
CS and CLK are interchangeable.
3
Returning CS HIGH avoids an additional “false clock” of serial data input.
4
Do not clock in serial data while LD is LOW.