Datasheet

DAC8420
Rev. B | Page 9 of 24
Table 6. Control Function Logic Table
CLK
1
CS
1
LD CLR
CLSEL Serial Input Shift Register DAC Register A to DAC Register D
NC
2
High High Low High No change Loads midscale value (0x800)
NC
2
High High Low Low No change Loads zero-scale value (0x000)
NC
2
High High
↑
High /Low No change Latches value
↑
Low High High NC
2
Shifts register one bit No change
Low
↑
High High NC
2
Shifts register one bit No change
High
NC (↑)
2
↓
High NC
2
No change Loads the serial data-word
3
High NC
2
Low High NC
2
No change Transparent
4
NC
2
High High High NC
2
No change No change
1
CLK and
CS
are interchangeable.
2
NC = Don’t Care.
3
Returning
CS
high while CLK is high avoids an additional false clock of serial input data. CLK and
CS
are interchangeable.
4
Do not clock in serial data while
LD
is low.