Datasheet

DAC8420
Rev. B | Page 7 of 24
CS
SDI
CLK
LD
DATA LOAD SEQUENCE
SDI
CLK
CS
LD
VOUTx
DATA LOAD TIMING
CLSEL
CLR
V
OUT
CLEAR TIMING
t
CLRW
±1LSB
t
S
t
LD2
t
CSH
t
CSS
t
LD1
A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0
t
DS
t
DH
t
CH
t
CL
t
CSH
t
LD2
t
LDW
t
S
±1LSB
0
0275-002
Figure 2. Timing Diagram
10kΩ
10µF 0.1µF
+10
V
1N4001
+
10kΩ
10µF 0.1µF
–10V
1N4001
+
10kΩ
10µF 0.1µF
+15
V
1N4001
+
10kΩ
10µF 0.1µF
–15V
1N4001
+
5kΩ
5kΩ
10kΩ
NC
NC
NC
NC
NC
NC = NO CONNECT
DUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0
0275-003
Figure 3. Burn-In Diagram