Datasheet

DAC8420
Rev. B | Page 20 of 24
89161514121110
DAC8420
DAC A
DAC B
DAC C
DAC D
4
5
DIGITAL
CONTROLS
GND
DIGITAL INPUTS
VREFHI
VREFLO
2
3
6
7
5V SUPPLY
VOUTA
VOUTB
VOUTC
VOUTD
00275-036
REF43
V
IN
GND
4
2
V
OUT
6
0.1µF
5V SUPPLY
2.5V
VSS
0.1µF
1
5V
0.1µF
3
C1
C2
C3
C4
2
1
14
13
5
7
9
11
4
6
8
10
12
CMP04
604Ω
5V
RED LED
604Ω
5V
RED LED
OUT A
OUT B
VINA
VINB
Figure 36. Dual Programmable Window Comparator
DUAL WINDOW COMPARATOR
Often a comparator is needed to signal an out-of-range
warning. Combining the DAC8420 with a quad comparator
such as the
CMP04 provides a simple dual window comparator
with adjustable trip points as shown in
Figure 36. This circuit
can be operated with either a dual supply or a single supply. For
the A input channel, DAC B sets the low trip point, and DAC A
sets the upper trip point. The
CMP04 has open-collector outputs
that are connected together in a wire-OR’ed configuration to
generate an out-of-range signal. For example, when VINA
goes below the trip point set by DAC B, Comparator C2 pulls
the output down, turning on the red LED. The output can also
be used as a logic signal for further processing.
MC68HC11 MICROCONTROLLER INTERFACING
Figure 37 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
port outputs the serial data to load into the SDI input of the
DAC. The port lines (PD5, PC0, PC1, and PC2) provide the
controls to the DAC as shown.
00275-037
DAC8420*
CLSEL
CLK
SDI
CLR
CS
LD
PC2
SCK
MOSI
PC1
PC0
(PD5) SS
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. MC68HC11 Microcontroller Interface
For correct operation, the MC68HC11 should be configured
such that its CPOL bit and CPHA bit are both set to 1. In this
configuration, serial data on MOSI of the MC68HC11 is valid
on the rising edge of the clock, which is the required timing for
the DAC8420. Data is transmitted in 8-bit bytes (MSB first),
with only eight rising clock edges occurring in the transmit
cycle. To load data to the input register of the DAC8420, PC0
is taken low and held low during the entire loading cycle. The
first eight bits are shifted in address first, immediately followed
by another eight bits in the second least-significant byte to load
the complete 16-bit word. At the end of the second byte load,
PC0 is then taken high. To prevent an additional advancing of
the internal shift register, SCK must already be asserted before
PC0 is taken high. To transfer the contents of the input shift
register to the DAC register, PD5 is then taken low, asserting the
LD
input of the DAC and completing the loading process. PD5
should return high before the next load cycle begins. The
CLR
input of the DAC8420 (controlled by the output PC1) provides
an asynchronous clear function.