Datasheet
DAC8412/DAC8413 Data Sheet
Rev. G | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
REFH
1
V
OUTB
2
V
OUTA
3
V
SS
4
V
REFL
28
V
OUTC
27
V
OUTD
26
V
DD
25
DGND
5
RESET 6
LDAC 7
V
LOGIC
24
CS23
A022
DB0 (LSB)
8
A1
21
DB1
9
R/W
20
DB2 10 DB11 (MSB)19
DB3 11 DB1018
DB4
12
DB9
17
DB5 13 DB816
DB6 14 DB715
00274-008
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
DGND
RESET
LDAC
DB0 (LSB)
DB1
DB2
DB3
V
DD
V
LOGIC
CS
A0
A1
R/W
DB11 (MSB)
V
SS
V
OUTA
V
OUTB
V
REFH
V
REFL
V
OUTC
V
OUTD
DB4
DB5
DB6
DB7
DB8
DB9
DB10
PIN 1
INDENTFIER
12 13 14 15 16 17 18
00274-009
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
00274-010
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
5
DGND
6
RESET
7
LDAC
8
DB0 (LSB)
9
DB1
10
DB2
11
DB3
25
V
DD
24
V
LOGIC
23
CS
22
A0
21
A1
20
R/W
19
DB11 (MSB)
26
V
OUTD
27
V
OUTC
28
V
REFL
1
V
REFH
2
V
OUTB
3
V
OUTA
4
V
SS
18
DB10
17
DB9
16
DB8
15
DB7
14
DB6
13
DB5
12
DB4
Figure 7. PDIP/CERDIP Figure 8. PLCC Figure 9. LCC
Table 5. Pin Function Descriptions
Pin Number Mnemonic Description
1 V
REFH
High-Side DAC Reference Input.
2 V
OUTB
DAC B Output.
3 V
OUTA
DAC A Output.
4 V
SS
Lower Rail Power Supply.
5 DGND Digital Ground.
6
RESET
Reset Input and Output Registers to all 0s, Enabled at Active Low.
7
LDAC
Load Data to DAC, Enabled at Active Low.
8 DB0 Data Bit 0, LSB.
9 DB1 Data Bit 1.
10 DB2 Data Bit 2.
11 DB3 Data Bit 3.
12 DB4 Data Bit 4.
13 DB5 Data Bit 5.
14 DB6 Data Bit 6.
15 DB7 Data Bit 7.
16 DB8 Data Bit 8.
17 DB9 Data Bit 9.
18 DB10 Data Bit 10.
19 DB11 Data Bit 11, MSB.
20
R/W
Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with V
LOGIC
connected to 5 V.
21 A1 Address Bit 1.
22 A0 Address Bit 0.
23
CS
Chip Select, Enabled at Active Low.
24 V
LOGIC
Voltage Supply for Readback Function. Can be open circuit if not used.
25 V
DD
Upper Rail Power Supply.
26 V
OUTD
DAC D Output.
27 V
OUTC
DAC C Output.
28 V
REFL
Low-Side DAC Reference Input.