Datasheet

DAC8408
–5–
REV. A
WAFER TEST LIMITS
at V
DD
= +5 V; V
REF
= 610 V; V
OUT
A, B, C, D = 0 V; T
A
= +258C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D.
DAC8408G
Parameter Symbol Conditions Limits Units
STATIC ACCURACY
Resolution N 8 Bits min
Nonlinearity
1
INL ±1/2 LSB max
Differential Nonlinearity DNL ±1 LSB max
Gain Error G
FSE
Using Internal R
FB
±1 LSB max
Power Supply Rejection PSR Using Internal R
FB
0.001 %FSR/% max
(∆V
DD
= ±10%)
2
I
OUT 1A, B, C, D
Leakage Current I
LKG
All Digital Inputs = 0 V ±30 nA max
V
REF
= +10 V
REFERENCE INPUT
Reference Input R
IN
6/14 kΩ min/max
Resistance
3
Input Resistance Match R
IN
±1 % max
DIGITAL INPUTS
Digital Input Low V
IL
0.8 V max
Digital Input High V
IH
2.4 V min
Input Current
4
I
IN
±1.0 µA max
DATA BUS OUTPUTS
Digital Output Low V
OL
1.6 mA Sink 0.4 V max
Digital Output High V
OH
400 µA Source 4 V min
Output Leakage Current I
LKG
±1.0 µA max
POWER SUPPLY
Supply Current
5
I
DD
50 µA max
Supply Current
6
I
DD
1.0 mA max
NOTES
1
This is an endpoint linearity specification.
2
FSR is Full Scale Range = V
REF
–1 LSB.
3
Input Resistance Temperature Coefficient approximately equals +300 ppm/°C.
4
Logic inputs are MOS gates.Typical input current at +25°C is less than 10 nA.
5
All Digital Inputs are either “0” or V
DD
.
6
All Digital Inputs are either V
IH
or V
IL
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.