Datasheet

DAC8248
–5–
REV. B
11. AGND 13. NC
12. I
OUTA
14. DB1
13. R
FB A
15. DB0(LSB)
14. V
REF A
16. RESET
15. DGND 17.
LSB/MSB
16. DB7(MSB) 18.
DAC A/DAC B
17. DB6 19.
LDAC
18. DB5 20.
WR
19. DB4 21. V
DD
10. DB3 22. V
REF B
11. DB2 23. R
FB B
12. NC 24. I
OUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY
CONNECTED TO V
DD
.
DICE CHARACTERISTICS
WAFER TEST LIMITS
@ V
DD
= +5 V or +15 V, V
REF A
= V
REF B
= +10 V, V
OUT A
= V
OUT B
= 0 V; AGND = DGND = 0 V; T
A
= 258C.
DAC8248G
Parameter Symbol Conditions Limit Units
Relative Accuracy INL Endpoint Linearity Error ±1 LSB max
Differential Nonlinearity DNL All Grades are Guaranteed Monotonic ±1 LSB max
Full-Scale Gain Error
1
G
FSE
Digital Inputs = 1111 1111 1111 ±4 LSB max
Output Leakage Digital Inputs = 0000 0000 0000
(I
OUT A
, I
OUT B
)I
LKG
Pads 2 and 24 ±50 nA max
Input Resistance
(V
REF A
, V
REF B
)R
REF
Pads 4 and 22 8/15 kΩ min/kΩ max
V
REF A
, V
REF B
Input ∆R
REF
Resistance Match R
REF
±1 % max
Digital Input High V
INH
V
DD
= +5 V 2.4 V min
V
DD
= +15 V 13.5 V min
Digital Input Low V
INL
V
DD
= +5 V 0.8 V max
V
DD
= +15 V 1.5 V max
Digital Input Current I
IN
V
IN
= 0 V or V
DD
; V
INL
or V
INH
±1 µA max
Supply Current I
DD
All Digital Inputs V
INL
or V
INH
2 mA max
All Digital Inputs 0 V or V
DD
0.1 mA max
DC Supply Rejection
(∆Gain/∆V
DD
) PSR ∆V
DD
= ±5% 0.002 %/% max
NOTES
1
Measured using internal R
FB A
and R
FB B
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Die Size 0.124 × 0.132 inch, 16,368 sq. mils
(3.15
× 3.55 mm, 10.56 sq. mm)