Datasheet

REV. B
DAC8043A
–4–
SRI
CLK
LD
SRI
CLK
LD
FS
ZS
V
OUT
DATA LOADED MSB(D11) FIRST DAC REGISTER LOAD
D11
D10 D9 D8 D6 D5 D4 D3 D2 D1 D0D7
t
LD1
t
DS
t
DH
t
CL
t
CH
t
LD
t
S
ⴞ1 LSB
ERROR BAND
Dxx
t
ASB
Figure 2. Timing Diagram
Table I. Control-Logic Truth Table
CLK LD Serial Shift Register Function DAC Register Function
u H Shift-Register-Data Advanced One Bit Latched
H or L L No Effect Updated with Current Shift Register Contents
L u No Effect Latched All 12 Bits
NOTES
u positive logic transition.
The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the
switches in the R-2R DAC ladder.
TOTAL UNADJUSTED ERROR – LSB
FREQUENCY
15
20
0
–1.0 1.0
10
30
–0.5 0.0 0.5
SS = 200 UNITS
T
A
= 25ⴗC
V
DD
= 5V
V
REF
= 10V
25
5
35
Figure 3. Total Unadjusted Error Histogram
Typical Performance Characteristics
FULL SCALE TEMPCO – ppm/ⴗC
FREQUENCY
30
20
0
0
10
40
50
SS = 200 UNITS
T
A
= –40ⴗC TO +85ⴗC
V
DD
= 5V
V
REF
= 10V
12
Figure 4. Full-Scale Output Tempco Histogram