Datasheet

DAC312
–13–
REV. C
DESCRIPTION OF OPERATION
The DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
The three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is con-
nected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the I
O
line, while all
higher order resistors (R6 through R8) are summed into the I
O
line. The R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the I
O
or I
O
lines depending on the bits selected. In the fig-
ure, the code selected is: 100 110000000. Therefore, 2 mA (4 ×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into I
O
giving an I
O
of 2.375 mA. I
O
has a current
of 1.625 mA with this code. As the three MSB’s are increment-
ed, each successively higher code adds 0.5 mA to I
O
and sub-
tracts 0.5 mA from I
O
, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. This configuration guar-
antees monotonicity.
Expanded Transfer Characteristic Segment (001 010 011)
Simplified Schematic