Datasheet

DAC312
–4–
REV. C
WAFER TEST LIMITS
DAC312N DAC312G
Parameter Symbol Conditions Limit Limit Units
Resolution 12 12 Bits min
Monotonicity 12 12 Bits min
Nonlinearity ±0.05 ±0.05 %FS max
Output Voltage Full-Scale Current +10 +10 V max
Compliance Voc Change <1/2 LSB –5 –5 V min
Full-Scale V
REF
= 10.000 V 4.031 4.063 mA max
Current R
14
, R
15
= 10.000 kΩ 3.967 3.935 mA min
Full-Scale Symmetry I
FSS
±1 ±2 µA max
Zero-Scale Current I
ZS
0.1 0.1 µA max
Differential DNL Deviation from ±0.012 ±0.025 %FS max
Nonlinearity Ideal Step Size ±1/2 ±1 Bits (LSB) max
Logic Input Levels “0” V
IL
V
LC
= GND 0.8 0.8 V max
Logic Input Levels “1” V
IH
V
LC
= GND 2 2 V min
Logic Input Swing V
IS
+18 +18 V max
–5 –5 V min
Reference Bias
Current I
15
–2 –2 µA max
Power Supply PSSI
FS+
V+ = +13.5 V to +16.5 V, V– = –15 V ±0.001 ±0.001
Sensitivity PSSI
FS–
V– = –13.5 V to –16.5 V, V+ = +15 V ±0.001 ±0.001 %/%max
Power Supply I+ V
S
= +15 V 7 7
Current I– I
REF
≤ 1.0 mA –18 –18 mA max
Power V
S
= +15 V
Dissipation P
D
I
REF
≤ 1.0 mA 375 375 mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
@ V
S
= 615 V, I
REF
= 1.0 mA, T
A
= 258C, unless otherwise noted. Output characteristics refer to both I
OUT
and I
OUT
.
DICE CHARACTERISTICS
DIE SIZE 0.141 × 0.096 inch, 13,536 sq. mils (3.58 × 2.44 mm, 8.74 sq. mm)
1. B1 (MSB) 11. B11
2. B2 12. B12 (LSB)
3. B3 13. V
LC
/A
GND
4. B4 14. V
REF
(+)
5. B5 15. V
REF
(–)
6. B6 16. COMP
7. B7 17. V–
8. B8 18. I
O
9. B9 19. I
O
10. B10 20. V+