Datasheet

DAC10
REV. D
–7–
Figure 15. Positive Low Impedance Output Operation
Figure 16. Negative Low Impedance Output Operation Figure 17. Interfacing with Various Logic Families
Figure 14. Settling Time Measurement
DAC10
E
OOP01
R
L
0 TO +I
FR
3 R
L
I
O
I
O
4
2
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO
I
O
(PIN 2); CONNECT I
O
(PIN 4) TO GROUND.
I
FR
=
1023
1024
3 2 3 I
REF
DAC10
E
O OP15
0 TO –I
FR
3 R
L
I
O
I
O
4
2
I
FR
=
1023
1024
3 2 3 I
REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO
I
O
PIN 2); CONNECT I
O
(PIN 4) TO GROUND.
R
L
ECL
13kV
–5.2V
V
LC
TO PIN 1
2N3904
"A"
39kV
3kV
6.2kV
2N3904
+15V
V
LC
9.1kV
V
TH
= V
LC
+1.4V
+15V CMOS
V
TH
= +7.6V
6.2kV 0.1mF
DAC10
TTL
V
TH
= +1.4V
V
LC
1
51
V
2.5kV
2.5kV
10kV
1MV
1/4W, 5%
CARBON
2kV
4kV
1kV
499kV
1/4W, 5% CARBON
0.01mF
1mF
0.01mF
0.1mF10mF
4.7mF
0.01mF
1mF
0.01mF 4.7mF
0.1mF10mF
+15V
V
L
0.500V 60.001V
+15V
–15V
V
O
–15V
+15V
15 16 18
3
17 1 2
5
14
4
2
6
5
4
REF-01
–15V
–15V
175mV
2N918
2N918
LOW-TO-HIGH SETTLING V
L
= 16.500V 60.001V
HIGH-TO-LOW SETTLING V
L
= 0.500V 60.001V
1/2 LSB SETTLING = 7.8mV
NOTES:
1. CASE OF 2N918s MUST BE GROUNDED.
2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.
3. USE FET PROBE (7A11 SCOPE PLUGIN).
D.U.T.
IN5711