Datasheet

DAC08
Rev. C | Page 12 of 20
00268-C-030
E
O
*OR ADR01
4
2
6
5
10kΩ
+15V –15V
–15V
+15V
5.0kΩ
15V
MSB
B1
B2 B3 B4 B5 B6 B7
LSB
B8
5.000kΩ
5.0kΩ
POS. FULL RANGE
ZERO SCALE
NEG. FULL SCALE +1LSB
NEG. FULL SCALE
B1
1
1
0
0
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
1
0
0
B6
1
0
0
0
B7
1
0
0
0
B8
1
0
1
0
E
O
+4.960
0.000
–4.960
–5.000
10V
REF01*
V
O
–V
4
2
I
O
I
O
V+
C
C
V
LC
AD8671
Figure 29. Offset Binary Operation
00268-C-031
I
O
R
L
I
O
E
O
0 TO –I
FR
× R
L
I
FR
= I
REF
255
256
4
2
AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC)
.
CONNECT INVERTING INPUT OF OP AMP TO I
O
(PIN 2): CONNECT I
O
(PIN 4)
TO GROUND.
Figure 30. Positive Low Impedance Output Operation
00268-C-032
I
O
R
L
I
O
E
O
0 TO –I
FR
× R
L
I
FR
= I
REF
255
256
4
2
AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC)
.
CONNECT NONINVERTING INPUT OF OP AMP TO I
O
(PIN 2): CONNECT I
O
(PIN 4)
T
O GROUND.
Figure 31. Negative Low Impedance Output Operation
00268-C-033
1
TTL, DTL,
V
TH
=1.4V
15V
9.1k
Ω
6.2k Ω
0.1 µ F
V
LC
13k Ω
39k Ω
ECL
"A"
3k
Ω
TO PIN 1
V
LC
6.2k Ω
–5.2V
20k
Ω
20k Ω
V+
"A"
3k
Ω
TO PIN 1
V
LC
R3
400
µ A
CMOS, HTL, NMOS
TEMPERATURE COMPENSATING V
LC
CIRCUITS
V
TH
= V
LC
1.4V
15V CMOS
V
TH
= 7.6V
V
LC
2N3904
2N3904
2N3904
2N3904
Figure 32. Interfacing with Various Logic Families