User manual

System Architecture
2-2 ADSP-BF538F EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
This EZ-KIT Lite is designed to demonstrate capabilities of the
ADSP-BF538F Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage of the processor is supplied by the internal voltage
regulator.
Figure 2-1. System Architecture
ADSP-BF538F
DSP
USB
Conn
Debug
Agent
JTAG
Conn
Power
Regulation
LEDs (6)
EBUI
JTAG
Port
+7.0V
Connector
32.768 KHz
Oscillator
RTC
SPIs
64 MB
SDRAM
(32M x 16)
Expansion
Connectors
(3)
4 MB
Flash
(2M x 16 )
25 MHz
Oscillator
UARTs SPORTs PBs (4)
RS-232
Female
RS-232
Interface
GPIO
CAN TWI
CAN
Transceiver
(2)
RJ10
(3)
SPI
Conns
PPI
Conn
Timers
Timer
Conn
(2)
TWI
Conn
(4)
SPORT
Conns
(3)
UART
Conns
ADC/
DAC
Stereo
In/Out
ELVIS
PPI