Datasheet
AN-1006 Application Note
Rev. A | Page 8 of 16
CYPRESS USB INTERFACE
The Cypress USB interface is the core of the system, including
all of the necessary functionality to convert USB commands
into corresponding I
2
C or SPI read/write transfers, and acts as a
FIFO to route data between the host PC and the target device.
CRYSTAL OSCILLATOR SCHEMATIC
The Cypress USB interface is its own clock master, and the board
includes a crystal oscillator circuit with a 24 MHz piezoelectric
crystal resonator to provide stability to the oscillator circuit.
The crystal resonator is driven in parallel by the XTALOUT
and XTALIN pins of the Cypress USB interface.
Y1
24.000MHz
C11
22pF
C27
22pF
08093-021
Figure 20. Crystal Oscillator Schematic
Local to 68053
C1
1.0uF
R5
100k
R6
475R
Y1
24.000MHz
C11
22pF
C27
22pF
C6
0.10uF
C4
0.10uF
+
C15
15uF
R15
49R9
D2
BLUE CLEAR
D1
YELLOW DIFFUSED
YELLOW DIFFUSED
D3
R7
475R
475R
475R
R8
R9
2D
AVCC
1D
AVCC
2F
1F
AGND
AGND
5A
VCC_IO
VCC_IO
VCC_IO
VCC_IO
VCC_D
VCC_A
5B
7E
8
E
5C
1
G
1H
GND
GND
GND
GND
GND
GND
GND
2H
4A
4B
4C
7D
8D
1E
DMINUS
2E
DPLUS
8B
RESET
1C
XTALIN
2C
XTALOUT
2B
CLKOUT
8G
PA0/INT0
6G
PA1/INT1
8F
PA2/SLOE
7F
PA3/WU2
6F
PA4/FIFOADR0
8C
PA5/FIFOADR1
7C
PA6/PKTEND
6C
PA7/FLAGD/SLCS
3H
PB0/FD[0]
4F
PB1/FD[1]
4H
PB2/FD[2]
4G
PB3/FD[3]
5H
PB4/FD[4]
5G
PB5/FD[5]
5F
PB6/FD[6]
6H
PB7/FD[7]
8A
PD0/FD[8]
7A
PD1/FD[9]
6B
PD2/FD[10]
6A
PD3/FD[11]
3B
PD4/FD[12]
3A
PD5/FD[13]
3C
PD6/FD[14]
2A
PD7/FD[15]
1A
RDY0/SLRD
1B
RDY1/SLWR
7H
CTL0/FLAGA
7G
CTL1/FLAGB
8H
CTL2/FLAGC
2G
IFCLK
7B
WAKEUP
3F
SCL
3G
SDA
U3
CYPRESS_CY7C68053_56BAXI
2
3
1
5
4
U4
FXLP34P5X
2
3
1
5
4
U5
FXLP34P5X
2
A
3
GND
1
5
VCCY
VCCA
4
Y
A
GND
VCCY
VCCA
Y
A
GND
VCCY
VCCA
Y
U6
FXLP34P5X
C9
0.10uF
C5
0.10uF
C10
0.10uF
C8
0.10uF
C12
0.10uF
R1
10k0
R2
10k0
GND
DPLUS
DMINUS
SCL
SDA
1DD8V3DD3V
CDATA
COUT
CLATCH1
CCLK
IOVDD
USB_CLK
IOVDD
BRD_RESET
IOVDD
3V3DD
CLATCH2
CLATCH3
CLATCH4
CLATCH5
USB_PWR_ON
3V3DD
3V3DD
3V3DD
IOVDD
IOVDD
IOVDD
3V3DDIOVDD
IOVDD
0
8093-020
Figure 21. Cypress USB Interface Schematic