Datasheet

SHARC Audio EZ-Extender Manual 2-3
SHARC Audio EZ-Extender Hardware Reference
Figure 2-2 is a block diagram of the audio interface; the diagram illustrates
how the serial ports are interfaced to the processor and AD1939 codecs on
a mating SHARC EZ-Board. The block diagram is a high-level diagram
and does not show the voltage translation circuitry or clock buffers. The
schematic pages are available in “SHARC Audio EZ-Extender Schematic”
on page B-1.
Figure 2-2. Serial Port Configuration Block Diagram
SPORT0_CLK
SPORT0_FS
SPORT0_DA
12.288MHz
OSC
ADSP-2146x
SPORT0_DB
AD193x [1]
DBCLK
DLRCLK
DSDATA1
DSDATA3
DSDATA2
DSDATA4
ABCLK
ALRCLK
ASDATA1
ASDATA2
MCLK
SPORT1_CLK
SPORT1_FS
SPORT1_DA
SPORT1_DB
SPORT2_CLK
SPORT2_FS
SPORT2_DA
SPORT2_DB
EZ-Extender operation: AD193x in Dual Line TDM Mode for 192kHz
operation w/ 12 ADC and 24 DACs.
AD193x [2]
DBCLK
DLRCLK
DSDATA1
DSDATA3
DSDATA2
DSDATA4
ABCLK
ALRCLK
ASDATA1
ASDATA2
MCLK
AD193x [3]
DBCLK
DLRCLK
DSDATA1
DSDATA3
DSDATA2
DSDATA4
ABCLK
ALRCLK
ASDATA1
ASDATA2
MCLK
SPORT3_CLK
SPORT3_FS
SPORT3_DA
SPORT3_DB
SPORT4_CLK
SPORT4_FS
SPORT4_DA
SPORT4_DB
SPORT5_CLK
SPORT5_FS
SPORT5_DA
SPORT5_DB
Codec (in white) is Master and also supports I2S operation