Datasheet

Software-Controlled Switches (SoftConfig)
2-10 ADSP-BF609 EZ-KIT Lite Evaluation System Manual
Page 12 of the “ADSP-BF609 EZ-KIT Lite Schematic” on page B-1
shows how the three Microchip GPIO expanders are connected to the
board’s ICs.
U41, a 10-bit bus switch, connects the link port 0 processor interface to J3
(link port connector) when the select input signal (pin 12) is high. By
default, the U41 select input is controlled by the boot mode switch (SW2).
When the boot mode switch is set to 1 (parallel flash boot), the select line
is high, enabling the system memory controller (SMC) signals, connected
through pins PA0-7 and PB0-1 of the processor. Setting the boot mode
switch to 6 (link port boot) drives the select line low and enables the link
port 0 connection to the J3 connector.
The U41 output selection, which is based on the boot mode selection, can
be overridden by the Microchip (U46) signal GPA0. This override is useful
in a case where the application needs to boot from parallel flash but then
use the link port 0 afterwards. After setting the signal high (to disable
U29), use GPA3 to control the output of U41.
The processor signals connected to
U41 can be disconnected from the link
port to support other features. The selection line must be low in order to
disconnect the signals from the link port connector
J3. This allows the
signals to connect to the on-board parallel flash memory and EI3 connec-
tors. See “ADSP-BF609 EZ-KIT Lite Schematic” on page B-1 for details.
Table 2-4. I
2
C Hardware Address 0x23
GPIO MCP23017 Register Address Default Value
GPIOA 0x12 0x00
GPIOB 0x13 0x00