Datasheet

System Architecture
2-2 ADSP-BF609 EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board (Figure 2-1).
The EZ-KIT Lite is designed to demonstrate the ADSP-BF609 Blackfin
processor’s capabilities.
The clock rate can be set up on the fly by the processor. The input clock is
25 MHz. The core clock runs at a maximum of 500 MHz. The default
boot mode for the processor is parallel flash boot. See “Boot Mode Select
Switch (SW2)” on page 2-19 for information on how to change the
default boot mode.
Figure 2-1. EZ-KIT Lite Block Diagram
ADSP-BF609
500 MHz
Dual Core
349-lead LFBGA
0.80mm 19x19mm pkg
JTAG
Port
25 MHz
Oscillator
Power
Regulation
SMC0
32 MB
Burst Flash
(16M x 16 )
CLK
JTAG
Conn
Quad SPI
Flash
32Mb
ADM3315
RS232
DB9
Conn
5V
PWR
IN
3.30V (Adjustable)
1.25V (Adjustable)
Expansion Interface III
PBs/LEDs
Ext
Clock
Test Point/
Crystal
128 MB
DDR2
(64M x 16)
DDR2
USB OTG
Circuitry
Ethernet
RMII
PHY
SD/MMC
Conn
Rotary
Encoder
Conn
ADM1032
Temp
Sensor
CAN
RJ11
Conn
TJA 1041
Transceiver
10/100
MAC
SPI
RJ45
CONN
USB
Mini
Conn
USB
2.0
(HS)
Temp
Sensor /
TWI
MMC
RSI
GP
COUNTER
GPIOs
CAN
2.0
UART
Link
Ports
1.80V (Adjustable)
Serial
Ports
EPPI
Ports
Link Port 0/
MPJTAG Out
Conn
DIP
SWTs
Link Port 1 /
MPJTAG In
Conn
EPPIs
UART
SPI
Power
ACM PWM
TWI
EBIU
Serial
Ports
GPIOs
USB
CLK
48 MHz
Oscillator
Ext
Clock
Test Point/
Crystal