Datasheet

ADSP-BF609 EZ-KIT Lite Evaluation System Manual 1-13
Using ADSP-BF609 EZ-KIT Lite
SPI Interface
The ADSP-BF609 processor has two SPI interfaces, SPI0 and SPI1. SPI0 is
connected to a Winbond W25Q32BV 32 Mb serial flash memory with
dual and quad SPI support.
Quad mode is enabled by default. The processor flag signals, PD00 and
PD01 (SPI0 D2 and D3), can be disconnected by using SoftConfig. Refer to
“Software-Controlled Switches (SoftConfig)” on page 2-3 for more infor-
mation. By default, the SPI0 chip select 1 is connected to the memory
device. This can also be disconnected by using SoftConfig.
SMC Interface
The Static Memory Controller (SMC) interface of the ADSP-BF609
EZ-KIT Lite contains a 32 MB (16M x 16) Numonyx PC28F128P33B
parallel flash chip. Flash memory is connected to the 16-bit data bus and
address lines 1–23. Chip enable is decoded by using SMC0_AMS0.
The flash memory is bottom boot and provides One-Time-Programmable
(OTP) memory.
Flash memory is pre-loaded with boot code for the POST program. For
more information, refer to “Power-On-Self Test” on page 1-20.
Ethernet Interface
The ADSP-BF609 processor has two Reduced Media Independent Inter-
faces (RMIIs), one of which connects to an external Ethernet PHY device.
The EZ-KIT Lite provides a National DP83848C, Auto-MDIX, fully
compliant PHY with IEEE 802.2/802.2u standards. The PHY supports
10BASE-T and 100BASE-TX operations. The PHY and processor support
IEEE 1588 time stamping, available on the EZ-KIT Lite via a standard